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Re: set up and hold time, transisitor level - explanation ne
there are two video lectures here (i'm sorry i don't remember which ones, but they are near the end of the course) that explain timing and where setup/hold numbers come from. it is interesting to learn that of course setup and hold...
Re: Difference between Divide by n counter and clock divider
shwetha100: i get it know. i think you're talking about a ripple counter as in
https://web.mit.edu/bunnie/www/xi/seminar/slide3.pdf. i was talking intially about a regular counter (simple fsm type where the current state is the...
if you draw an nmos with its source and gate (input high/switch on)connected to Vdd, and adjust the voltage of the drain (the output), you'll see that once the drain gets higher than Vdd - Vth the nmos will turn off. This means the output can never get higher than Vdd - Vth. It's still a 1 if...
Re: Antenna violation questions (metal jogging, diode insert
presumable drawbacks i can think of off the top of my head:
1) area: antenna diodes take up area
2) speed: they add a diffusion capacitance to the net they're attached to
Re: Difference between Divide by n counter and clock divider
shwetha100: what you're describing is called a "shift register" not a counter. you can also divide the clock with the circuit you described, but it will by a %50 div by 6 clock.
the best way to figure out how it works is to to draw...
Re: Difference between Divide by n counter and clock divider
the counter just counts. for instance in your example of counting up to five, you'll need a 3 bit counter, then when it reaches the value 3'b101 some combinational logic will go high (output will be a divide by five clock signal with...
Re: Antenna violation questions (metal jogging, diode insert
One reason you might do metal jogging instead of diode insertion is if you're doing an ECO and you're not allowed to make any changes to the base layer and there aren't any spare cell antenna diodes lying around.
I didn't notice this was a latch the first time through. So it's a latch with a 0 delay inverter between it's output and input. Then the pulsewidth of the transparent level needs to be at least Tclk-q (measured from the opening edge) + Tsetup (measured from the closing edge) and the opaque level...
Re: Electronic faucet
What is an electronic faucet? Do you mean the kind that turn on when you place your hand under them? That's not really an ASIC question, as it's more to do with proximity sensors. Perhaps ask in the regular electronics forum?
I'm not %100 positive, but i'm pretty sure that compiler directives (like `define) get handled in a preprocessing step analogous to #define macros in C. if that is the case then the preprocessor is only looking for compiler directives and could care less about the other Verilog language...
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