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Recent content by deepakagarwal

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    how to compile files in a library (Xilinx)

    for compiling different file locating in different library you have to change library .... coz we can compile only those file which are located in present library....
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    VHDL interview questions

    vhdl interview questions with answers you can find similar questions on asicbank.com or vlsibank.com, asicworld.com... lots of websites are there.... just go to google and type Frequently asked question in VHDL... you will find the similar results regards Deepak
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    how to split bus going to different blocks?

    how to splir a bus in vhdl its depend s on HDL ... if you are using VHDL then you can use alias keyword... for ex.. IR : std_logic_vector(18 downto 0) and you want a variable rd1_erg which should be a part of IR from 11-13 then you can declare this as like alias rd1_reg:reg_addr is IR(13...
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    How to create the SDF & VHDL netlist for ModelSim SE 5.7

    too many port connections. modelsim no you dont have to modify your test bench for post par.....just call .sdf file in model sim....procedure you can find in Help menu ... coz this depends on your version....let me know if you r facing any problem after doing this ....
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    wat does 65nm 90nm mean

    it is refers to the Lmin used in the CMOS .... 65nm means d min length of d cmos gate is 65nm.....
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    Why Hold time does not depend on frequency?

    Hold Time hi i have some confusion regarding hold time violation... i have asked to several person for that one. whether we can remove hold time violation by increasing/decreasing frequency. all d person told me different answers. some told me we can... but some told me we cant... can any...
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    using logic in place of tristates

    you can use Mux correct me if i am wrong.
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    USEFUL BOOKS FOR UNDERSTANDING VLSI CONCEPTS

    For basics you can refer CMOS neil weste but if you want to make good concept and deep study then refer Digital integrated Circuit by John M Rabbey. That is very good book. but if you dont know basic concept of CMOS , better you first go through neil weste then after read rabbey.
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    Looking for information about bidirectional buses

    Bidirectional bus? bidirectional bus is used for transferring data to both side.... but if you tell us what you want ... then i can tell you specifically.
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    Info about antenna effect on gate strength and diffusion strength

    Antenna Effect antenna effect refers Its occuring during manufacturing proccess. Antennae are floating conduction layers without shielding layer of oxide [16]-effects poly and metal layers The random discharge of the floating node could permanently damage the transistor The best solution...
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    What is the best software to run Verilog code??

    Verilog Model Sim is d best tool for both HDL (VHDL , Verilog) and this tool is used in most of the companies...but with the command line version...
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    How to decide the width of core ring and power stripes?

    Power Planning that widths are provided in the project ...as an constraints... if you are doing just only practice on any tool then you can give by default value that will be given in the manual....
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    Documents about Clock Tree Synthesis

    Clock Tree Synthesis clock tree synthesis document you can get from nay synthesis tool like MAGMA.... FPGA tools ... in the help menu...
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    Questions about CMOS inverter output waveforms

    cmos question for the 1 and 2 case. its depends on RC delay... larger the capacitance larger the delay so delay for second case will be more..
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    Need information about DFT [ Design for Testability ]

    hi for the quick notes you can refer john m rabbey ... last chapter.. its very good and given a brief overview about DFT.

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