Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
This is no instance, no delay but just arrival and required time of the first timing arc in Innovus post-route timing report.
Could I ask where the arrival and required time come from?
Attached are the timing report and the applied sdc file generated from Genus.
Thanks!
Hi,
Thanks for the useful information!
I tried to rewrite my sdc file with different clock frequencies and found that whatever the clock frequency is, the negative timing slack is always -19ps at the first timing arc. It's really interesting. The timing reports in Genus and Innovus are as...
Hi,
During synthesis using Genus, timing is met with around 1ns positive slack while before placement in Innovus, timing is violated with around 10ps negative slack. Could I ask what's the possible reason for this?
I'm using GF22nm technology and the SDC file is as following...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.