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Most basic synthesis tools (Xilinx ISE, Design Compiler, etc.) will not automatically synthesize % or DIVIDE (/).
Synopsys sells an enhanced arithmetic library (DesignWare Foundation) for the Design_Compiler product. If you have the DW-Foundation (DWF) license, then you can directly synthesize...
What do you mean by "too many gates"? For each arithmetic operation in your RTL-code, Design-Compiler will allocate/create 1 Designware instance to implement it. A compare-operation (<, >, <=, >=) will use slightly fewer gates than a conventional adder, because the compare-output is just a...
> 1. ... can I use "*" directly in my RTL code for Design Compiler synthesis?
Yes, the basic version of Design_Compiler will automatically turn the "*" operator into a DesignWare component. If you have more advanced DC license (like DC-Ultra, or Designware-Foundation), then the speed/area of...
Re: ATPG question
> im talking about equipment thats implemented on the chip.
Your question isn't very clear.
In traditional SCAN/ATPG methodology, the test-patterns come from an external device (test-console.) The on-chip hardware is very limited -- 1) some I/O drivers to receive the...
tsmc memory
> How do you create ram based memories in TSMC flow.
You have 2 choices:
1) Make your own (study some VLSI and layout, then do your own layout)
2) Acquire a pre-designed/verified RAM-macro from an IP-vendor
There are several IP RAM/ROM vendors who target TSMC's foundry: Artisan...
dual port memory artisan
I thought TSMC doesn't provide anything. TSMC contracts with Artisan Components, who develop and release standard-cell library kits for many TSMC tech-nodes (0.25u, 0.18u, 0.15u, 0.13u, etc.) Are you talking about the automated Artisan RAM-compiler? The automated...
> however u can get a free version of that by the name of whitebox enterprise linux 3.0 (this is developed from the source of RHEL3.0). one thing is RHEL3.0 is not free. i'm using that for quite something, didn't find anything wrong with that.
The cost of RHEL is inconsequential compared to a...
Re: Reset pin
I believe that only works on asynchronous set/reset flipflops. For fully synchronous flops (no async inputs), there is no removal/recovery arc. And the synchronous set/reset pins aren't distinguishable from the data pin. But I suppose that depends on who generated your...
how to read bitmap image in verilog
> Modelsim provides very good integration with tcl/Tk you can use that for
displaying the images directly. For this you dont need any PLI stuff!
How hard is it to display a bitmap image using Tcl/Tk? Can this be done in other simulator-environments (like...
I would go even further to say that most Verilog simulators still don't have 100% Verilog-2001 support. But they've come a long way since 3 years ago, and it seems that the major vendors have implemented the most useful/requested features of Verilog-2001.
I assume the adoption of SystemVerilog...
> how to deal with test SE pin in scan mode when do sta?
In scan-mode, are you simulating a "load/unload" or a "capture" cycle? Depending on your DFT-insertion tool/methods, there may be timing differences between the capture and load/unload cycles, so it's best to analyze them separately...
For standard-cell digital-design (Verilog/VHDL), more interconnect layers loosely translate into "higher utilization" (gate-density.) Like you said, theadditional layers give the router-tool more "degrees of freedom" to connect gates to each other. As a side-effect, due to tighter packing of...
Re: Structured ASIC
> what is maent by structured ASIC and mask programmable cells in structured ASIC?
Structured ASICs are often compared to "standard-cell" ASICs. In standard-cell ASICs, the customer has complete freedom to implement all "layers" of wafer (logic, interconnect, via, etc.)...
I don't know the answer to your first question, but for your second question...
The "correct values" are totally dependent on your target technology. Each foundry library will have different recommendations for optimal synthesis quality.
The information you seek should be in your foundry's...
While I'm sure they're some books that overview the design-flow from gates -> GDSII, that's mostly theoretical because back-end design is set by a) Foundry and b) tool vendor. (Implementation of back-end varies from foundry to foundry, and from tool to tool.)
Hint: At 130nm or below, you must...
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