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Recent content by dazzling_deepika

  1. D

    size of sram pull up transistors

    I have read some where that the pull up transistors should be weak...why is it so?
  2. D

    SRAM layout question - which metal layers ?

    SRAM layout question In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
  3. D

    What is the Depth of Fifo...?

    is the answer to this deisgn problem : no fifo required
  4. D

    Interview question about a FIFO depth

    i have a question that is asked in an interview . i am writing into fifo asynchronously with 25 writes per second and reading form fifo with 25 reads per second synchronously. then what the depth of this fifo? My answer is no fifo required..am I correct?if not please explain the right ans
  5. D

    unsigned numbers question

    Suppose A,B,C are unsigned 32-bit numbers. How many bits are needed for Y = (A*B) + C?
  6. D

    hold time dbt - need explanation of a sentence

    Re: hold time dbt hi, I am sorry but I do not understand one thing:you are talking about edges x and x+1 .How can these be the same edges?
  7. D

    hold time dbt - need explanation of a sentence

    hold time dbt Can some body plz explain the following to me : because the launch edge and the capture edge is the same edge, the hold timing check doesn't depend on the clock period. how can launch edge and capture edge be the same for hold time?
  8. D

    Setup and Hold time violations

    Re: CROSSTALK even i want an answer to the question...how will victim be effected if the aggressor switches in the same and different direction?
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    clock jitter and hold time

    jitter hold setup I read some where that clock jitter does not effect hold time violation..is it true?if yes then why?
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    capacitance between interconnect

    HI, I come across this question at several places but never got the right answer: there are 3 parallel layers of metal interconnect and all three of them are switching as below: case1:the middle interconnect is switching in one direction(say 0 to 1) and the outer 2 interconnects are BOTH...
  11. D

    capaticance between interconnect

    capaticance HI, I come across this question at several places but never got the right answer: there are 3 parallel layers of metal interconnect and all three of them are switching as below: case1:the middle interconnect is switching in one direction(say 0 to 1) and the outer 2 interconnects...
  12. D

    Fundamental of digital circuits

    how to log onto eetop I am sorry but I did not get what an eetop means..is it a website ? Can you please give me the link to the book if u hv it..thanks a lot for the help
  13. D

    fundamental of digital circuits

    Where can I download Fundamental of digital circuits by A.Anand ebook. I need it urgently for an interview.
  14. D

    Fundamental of digital circuits

    fundamental of digital circuit Where can I download Fundamental of digital circuits by A.Anand ebook. I need it urgently for an interview.
  15. D

    why is inductance not considered?

    y is inductance not considered anywhere in digital design(layout,delay estimation,etc)?
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