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You are absolutely correct. I am also surprised it never complained and went straight though "Implement Design" without any issues. I really feel that VHDL is strongly typed but then Xilinx breaks that by not checking all aspects of the design being implemented for hardware. So what it actually...
Hey guys so my semester is wrapping up and fortunately I have gotten all of the projects for the class done. Now this is a simple question. Xilinx is issuing a warning but it doesn't seem to be enforcing what it says. More specifically I have no idea why it is even stating it in the first place...
Thanks that seems to work. I think I get it... that I need to use a process block. Wow this is starting to get a bit hard to comprehend on complex designs. Oh well.
I have another question... is there a way to declare a -new- logic vector in-line with an expression so I don't need to declare...
With your suggestion I synthesized it and got the warning:
:1369 - "C:\Users\DarkPrince\Documents\Xilinx\Lab2_SimpleALU\SimpleALU.vhd" Line 154: Possible infinite loop; process does not have a wait statement
I haven't tried it yet, in the middle of lecture, but will later. What I don't...
Hey everyone. I have a few more questions regarding VHDL and the quirks it seems to come with. I am -still- working on the ALU design that I posted about before but I changed my approach quite a bit. Eventually I will have to give up and declare everything manually but I wanted to make the...
Thank you Tricky, good reference and some of those attributes I didn't know about. Appreciate it. It looks like permute was rights, it is just a case of the indexies being rearranged before the for-loop so the logic behind it wasn't valid anymore. I normalized the inputs to the Add function and...
This idea of being able to reverse the indexing order is very disorienting and I think that is what I am getting stuck on. I just seem to have an issue wrapping my head around the behavior of the system when using "to" and "downto" interchangeably. I mean, I am just trying to get the concept...
Thank you for the support so far. It has been an interesting thought process wondering how to handle VHDL's ability to have arbitrary indexing (start and stop). Good thought about normalizing the vectors. As stated before this is an educational construct but will keep that in consideration for...
So I am having an issue wrapping my head around VHDL and lately been beating my head against a snippet I have made. I will be straight out with you this is an assignment for my class, but I am not asking for a solution, just for some help. I seem to be missing how my code is being synthesized...
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