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Recent content by danielkonduru

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    i need UART ip core for xa6slx45 device

    hai, I am in need of a UART ip core in my project. The UART should have programmable baud rate, and modem control. If there is any such code available? If the code isn't there can I atleast get the reference design and one more thing is it possible to implement 20 different uart ip cores in...
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    which xilinx ise tool is support for spartan6 fpga

    Hi all, what ISE design suite would be most optimal for use of startan6 fpga. I currently have 10.1 installed, but someone said 13.2 is really good. Any advice? thnx!
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    how to divide 40MHZ clock pulse to 44.24 KHZ and 18 KHZ

    thank you all. how to instantiate dcm's in spartan3e fpga using vhdl
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    how to divide 40MHZ clock pulse to 44.24 KHZ and 18 KHZ

    please help me how to divide clock iam using vhdl in fpga and by using dcm's is better or not and how to use dcm's please help me thanks.
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    clock division of 40 Mhz input clock to 44.24 khz

    please help me i am very beginner......... in my project two specificatons are required 1 is 22.6us and 2nd is 56us clock period . but in my project 40 mhz clock form crystal. please help me how to divide clock to get above specifications. thanks
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    [MOVED] how to get job in vlsi design

    hi all, this is prem kumar amd i completed b-ech in eee and i did a course in vlsi design. please help me how to get a job in vlsi domain. an dmy mail id is : danielkonduru@gmail.com
  7. D

    hi

    this is prem kumar how to get vlsi trainee job. i did course in vlsi design. please help me and my id is danielkonduru@gmail.com. thankyou

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