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I implemented ring oscillators on an Altera Cyclone IV with Quartus II.
The compilation choses arbitrarily which inputs of the LUTs are used.
I could edit each LUT seperatly but this is very time-consuming.
Is there a way to determine which LUT inputs are used without changing each one severally?
I put the inputs and outputs in relative postitions to the ROs. Although I set the involved partions to Post-Fit, the routing still changes after a new compilation (if there are changes made in the Chip Planner).
Is there a way to completly fix the routing between two Logic Lock Regions or...
The RO's internal routing is fixed. The routings of the connections of inputs and output depend on the design.
I want to use those variations for physical unclonable functions, but the frequency differences depending on the designs bother me.
That's what I feared.
I implemented ringoscillators (ROs) on a FPGA with a fixed position on the Logic Element level to analyse their oscillation frequency.
Depending on where I put the control logic (without moving a single cell of the ROs), the frequencies of each RO changed.
Take a look at the attachment file. The...
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