Power Supply on Cyclone IV

[d0nathan]

I implemented ringoscillators (ROs) on a FPGA with a fixed position on the Logic Element level to analyse their oscillation frequency.
Depending on where I put the control logic (without moving a single cell of the ROs), the frequencies of each RO changed.
Take a look at the attachment file. The green and red dots show the mean frequency (over some rounds and some fpgas) of 80 ROs.

I'm pretty sure that the lower frequencies arise from a lower power supply and the higher frequencies from a higher one. This seems to be depending on the routing for each design.

Is there a way to see how single LEs are connected to the power supply in the chip planner?

The basic question is:
How is the power supply realised for the LABs and LEs on Cyclone IV?

 

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I implemented ringoscillators (ROs) on a FPGA with a fixed position on the Logic Element level to analyse their oscillation frequency.
Depending on where I put the control logic (without moving a single cell of the ROs), the frequencies of each RO changed.
Take a look at the attachment file. The green and red dots show the mean frequency (over some rounds and some fpgas) of 80 ROs.

I'm pretty sure that the lower frequencies arise from a lower power supply and the higher frequencies from a higher one. This seems to be depending on the routing for each design.

Is there a way to see how single LEs are connected to the power supply in the chip planner?

The basic question is:
How is the power supply realised for the LABs and LEs on Cyclone IV?

Have you verified that the routing is identical for every instance of the RO that you've built in every case? Both relative placement and routing would have to be identical, besides that there will be process variations across the die.

As to the power question, I highly doubt there is anyone on edaboard (unless they work in the backend flow for Altera) that would know what the power distribution network metal layer looks like in Altera's parts. If you want that kind of detail you'll have to contact an Altera FAE, who in turn will have to contact the factory, which will likely reject the inquiry as proprietary information.

 

[d0nathan]

Have you verified that the routing is identical for every instance of the RO that you've built in every case? Both relative placement and routing would have to be identical,

The RO's internal routing is fixed. The routings of the connections of inputs and output depend on the design.

besides that there will be process variations across the die.

I want to use those variations for physical unclonable functions, but the frequency differences depending on the designs bother me.

As to the power question, I highly doubt there is anyone on edaboard (unless they work in the backend flow for Altera) that would know what the power distribution network metal layer looks like in Altera's parts. If you want that kind of detail you'll have to contact an Altera FAE, who in turn will have to contact the factory, which will likely reject the inquiry as proprietary information.

That's what I feared.

 

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The RO's internal routing is fixed. The routings of the connections of inputs and output depend on the design.

You should also isolate the routing for the input/outputs, by inserting a LUT in the path that has a fixed relative location for all ROs. You would end up with net loading issues that would affect the RO frequency without that isolation LUT.

 

[d0nathan]

You should also isolate the routing for the input/outputs, by inserting a LUT in the path that has a fixed relative location for all ROs.

I put the inputs and outputs in relative postitions to the ROs. Although I set the involved partions to Post-Fit, the routing still changes after a new compilation (if there are changes made in the Chip Planner).

Is there a way to completly fix the routing between two Logic Lock Regions or inside one LLR?
I found out I could use "Back-Anotate Assignments" and then the created rcf-file. But this seems quite complicated. Is there an easier way?