Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Two regs(count and pwm) are not initialized, you should use a reset signal to give the two regs initial values.
In real design, your code may be work, but in simulation, you will get x on the output.
- - - Updated - - -
Two regs(count and pwm) are not initialized, you should use a reset signal...
I am using Actel's A3P250 FPGA in my project. The chip I am using is -Std speed grade, but in Synplify and Designer I set the speed grade to -2. After I downloaded the program, it seems work well.
I wonder how does speed grade selection affect the compile result? Or does it only affect the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
