Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by complex

  1. C

    question about clock tree

    clock A is input clock, clock B is divided from clock A, where does the clock tree set?
  2. C

    how can I solve this problem

    hi,all there are two blocks, block A and blocks B,block A's clock is clka, and block B's clock is clkb. block A generates a ready signal to block B, and when block B receive the ready signal , it genetates a acknowledege signal to block A. the question is how to realize the signal ready and...

Part and Inventory Search

Back
Top