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Recent content by cmos80

  1. C

    Gate-charge simulation in hspice

    basically, i want the voltage to stop climbing when it reached maximum vg value to match my measurement data. any method to achieve this? Pls help!! thanks!
  2. C

    can anyone recommend a foundry support +500V process?

    how about vanguard? taiwan fab
  3. C

    Gate-charge simulation in hspice

    In this simulation, the key is the gate capacitance which is defined by the tox and tox has a default value. So, i don't think this is the reason for the simulation not running correctly. Is there any kind soul can debug my netlist? thank you!
  4. C

    help need~~~~~about HV process

    Vanguard has HV process up to Vgs 40V
  5. C

    help on use nwell resistor

    XRD1 VOUT VDD VDD NWELL R_LENGTH=50U R_WIDTH=5U is the correct way.
  6. C

    Hspice error: rsppo not found

    Re: Hspice error make sure the resistor library for rsppo is included
  7. C

    What is BCD process ?

    The main concerns will be spelt out in the design rule. But one thing to note will be the latch up problem in BCD and BiCMOS processes.
  8. C

    Gate-charge simulation in hspice

    Could someone please help me with the gate-charge simulation netlist? Trying to use 2 fixed current source ig & id but I encountered 2 problems: 1) vd vs charge, vd rises initally before decreases as expected 2) vg does not level at maxVg=6V Thank you in advance! ******* QG Simulation...

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