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Dear Jrom,
I reply you quite fast. I hope these reply are clear enough, if not I will edit the text to clarify. Also, if any of this explanations are not ok at all don't hesitate to correct me.
Thank you in advance.
1- Because of the source connected to V7 and the gate connected to V3, M8 and...
Hi,
As first step I highly recomend you to dominate the content of these books:
Design of Analog CMOS Integrated Circuits by Behzad Razavi, for analog VLSI design.
CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker, for digital VLSI design.
The Art of Analog Layout, by Alan...
Dear Joost,
I have some questions and recomendations:
- Why you use the V11 source on M4 and not connect a NMOS transistor between M1 and M7 to keep the symmetry?
- Think about why you implement the R9 resistor. Maybe you can use a second NMOS transistor to have a higher output impedance...
If you work with straight lines connections there's no difference. But, if you are going to have any corner in your routing, you will need a number of rectangles (r) similar to the number of corners, while the path (p) will be only one geometrical polygon.
In order to re-route or modifie the...
If you do not wanna these automatically placed metals in a specific area you should use the "no fill" layer in Cadence layout editor.
In my opinion, you should do this before the fabrication. Now, if you want to eliminate that metals, you should remove the pasivation and perform a wet etching...
Of course you can. For example, there are some situations where you need high resistance transistors in a small area. Then you can implement the W/L being the width times smaller than the length.
Dear Ahmed,
If you want to etch a zone of your chip in order to make your custom sensor or device you must be sure of this:
First, your design must include an open window in the passivation layer. This provides an access to the volume of oxide or metal that you need to etch before reaching the...
Dear junsik,
I will try to be brief and clear.
The pasivation can be eliminated via a controled RIE plasma etching (https://en.wikipedia.org/wiki/Reactive-ion_etching). This process is only accesible to clean room technicians.
The Aluminium and Tungsten used for the metal and via levels...
Dear Shemo:
The purpose of these transistors is biasing the gates of the m5, m6, m3 and m4. The main objective of this configuration is to increase the impedance of the vop and vom nodes.
Greetings.
At the end I used this solution:
Extract the circuit netlist and then using the command spectre_encrypt hide/encrypt the content of the netlist.
Greetings and thanks for all.
Thank you very much erikl!
But I have a schematic/layout design, I think that I can not create a Verilog-A model from the schematic/layout-extracted. Is there another solution?
Greetings and thanks in advance!
Hi to all!
I have been designing an amplifier + Test Buffer (50 Ohm) for a company and now I have to send my first results. This design has been developed in cadence.
My question is:
Is there any way to create a symbol that reproduces the circuit behavior but hides the netlist?
Greetings...
This circuit is discussed in chapter 4 of the book Analog Design for CMOS VLSI Systems / Franco Maloberti.
4.2.3 Self Biased Micro-Current Generator
4.2.4 Start-up Circuits
* There is an error in the above scheme. The correct scheme is attached.
Hi,
If you need a simple Current Source Reference independent of the supply voltage you can use the following scheme:
On the left the starting circuit is shown. The reference source circuit is on the right. Iref is the output current.
Greetings, I hope it meets your expectations.
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