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Hi to all,
I am mainly a software developer and I do not old with VHDL.
I have a doubt with functions in VHDL.
I wrote my complex function in vhdl (with some for..cycle internal) and I "recall" this function from my VHDL code, when I am in a determinate state of a my FSM.
My function is...
Thanks KlausST and dick_freebird for response.
I don't want to sound too pedantic, but I did a little experiment (my doubts arise from this).
I made a static memory cell on the breadboard, with two not (I used a 74HC04). after setting the logic state 0 at the input, I leave the input wire free...
Ok, I now have understand!
But now I have another doubt: in the dynamic RAM cell, when the capacitor is disconnected from others circuits, it is in floating state? If it is true, in this case the static electricity is influent?
Ok, but when two pass-transistor are off, the Input/output of the two NOT gate are floated and therefore subject to static electricity, there are no circuit protecting them...
Could this mean anything?
I have a question about static memory.
The classic circuit foresees that a static memory cell is formed by two NOT gates as shown in the figure:
My question is: when the pass gates (T1,T2) are off, could the static electricity present in the environment near the chip change the state of the...
Hi to all,
Ok, I have discovered that a my function work when I do:
function myConvert (A : in STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ) return integer is
variable output : integer := 0;
begin
output := 5;
return output;
end function;
But, it do not work when I do:
function myConvert (A : in...
Hi see these documents:
https://pinouts.ru/Memory/Simm72_pinout.shtml
https://allpinouts.org/pinouts/connectors/memory/dram-simm-ecc-72-pin/
PIN 19 is Not connected or is Address10?
PIN 29 is Address11 or Data16?
PIN 41 is /CAS1 or Address10?
And so on..
Hi to all,
I do not understand what is the correct pinout of the old 72 pin SIMM memories, some of the documents that I have found are conflicting for some PINs.
I am creating a project to drive several SIMMs with one FPGA, could you show me some reference scheme?
Yes, OK.
I would like to get a behavior like the one described by the simulator, in particular that the mosfet does NOT lead when Vgs is equal to GND.
So I should choose a MOSFET with a fairly high Vth. Could you suggest such a component?
If I understand well, for P-MOSFET, the Vgs should be less than Vth:
Vgs < Vth
When I connect my gate to Vdd I have Vgs = 0V
When I connect the gate to GND, Vgs = -3.3V
When I connect the gate to Vss, Vgs = -6.6V
It is correct?
In this case, my Spice model have than VTO = -3.55V. If I...
In this simulation (I am using multisim 14.0), the output voltage value (measured from XMM1) multimeter is:
~0V when S1 is on VDD
~0V when S1 is on GND
3.3V when S1 is on VSS
But, if I make this circuit on Breadboard whit a real VP0808, it do not faithful to simulation (I have 3.3V when S1...
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