Question about static RAM

[clros]

I have a question about static memory.
The classic circuit foresees that a static memory cell is formed by two NOT gates as shown in the figure:

My question is: when the pass gates (T1,T2) are off, could the static electricity present in the environment near the chip change the state of the stored bit, inducing a voltage?

 

[dick_freebird]

No, because the memory cells sit behind a wall of
input / output buffers, read / write circuitry etc.

Close-in fields are dominated by local cell signal
and power over which remote charge has no authority.

Only if the static electricity is discharged directly into
some pin and causes a write event, or buggers the
address during a write event, or drops the chip power
below retention voltage or above damage voltage,
would there be a possibility of bit-flip. Static as in just
sitting there, does nothing.

About the only way to flip a core memory cell is a
neutron, proton or heavy ion strike. Neither is likely in
a low altitude terrestrial application. Though neutrons
through nuclear reactions or knock-offs, at high altitude,
have been a problem for aviation and server farms.

 

[clros]

Ok, but when two pass-transistor are off, the Input/output of the two NOT gate are floated and therefore subject to static electricity, there are no circuit protecting them...
Could this mean anything?

 

[dick_freebird]

They are not floated, they are each driven by the other's
output. Positive feedback with high noise margin. And
several "layers" distant from any access from outside.
The switches attach the latch-pair to a higher-drive
complementary signal-pair which overdrives them
to the desired state. When off, they just drive each
other to the rails where they sit at negligible current.

 

[clros]

They are not floated, they are each driven by the other's
output.

Ok, I now have understand!

But now I have another doubt: in the dynamic RAM cell, when the capacitor is disconnected from others circuits, it is in floating state? If it is true, in this case the static electricity is influent?

 

[KlausST]

Hi,

you may call it floating ... but still there is a big enough capacitor not to change charge / state by external influence.

And since it is floating it may lose it´s charge / state after some time. Thus you need to regurarily "refresh" the charge of the capacitor.

Klaus

 

[clros]

Thanks KlausST and dick_freebird for response.

I don't want to sound too pedantic, but I did a little experiment (my doubts arise from this).

I made a static memory cell on the breadboard, with two not (I used a 74HC04). after setting the logic state 0 at the input, I leave the input wire free and if I bring an electrostatically charged pen close to the input (without touching it), the state changes.
I verified the change of state with an LED, which, when the pen approaches the input wire, turns on and stays on.

Why does this happen?

 

[KlausST]

Hi,

Generally a breadboard is not suitable for ESD tests.

If doing ESD tests you first should design your circuit according ESD rules.
It´s no suitable ESD test to bring an ESD charged "something" directly to an logic input.

It´s like doing a car brake test on ice... for sure the car won´t stop within the desired time.

Klaus

 

[FvM]

Clros, I suppose you're trying a shot in the dark without actual knowledge of DRAM cell geometry and electrical parameters. The points mentioned by dick_freebird in post #2 also apply to the sensitivity of DRAM cells against external fields. There's no chance to affect the memory content by expectable external field strength. ESD can be a problem if hitting the RAM device electrical terminals.

 

[dick_freebird]

The bench experiment with the inverters and
a long wire on a floating input, is not the same as
what an internal memory cell with its positive
feedback and nonzero drive strength will see.

If you have the charge to slew the input capacitance
and apply it fast enough that it overruns the inverter
drive strength, you can flip the latch same as any
other applied signal.

Now if you left a SRAM I/O pin open, you could induce
similar errors (as seen through the inputs >
memory array >outputs). But you just do not have
that "access" to the memory array itself. You can't
apply the signal to the part of it that you're talking
about.