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Recent content by chody

  1. C

    Pass through SSCG loop bandwidth in PLL and Oscillator Ques.

    what is sscg Hi, friends, What is the loop band width of PLL for pass through SSC(spread spectrum clock) with modulation frequency? For example, the general PLL's loop band width is 1/10 of reference clock. And, in current starved oscillator, is there the schem. that doesn't have resistor in...
  2. C

    What's the methods to simulate Phase Noise of PLL?

    Hi friends, If u want to see eye diagram of pll in HSPICE easily, use cosmo scope(or called cscope). PN(phase noise) u said, is shown as jitter of PLL, so u will see the jitter through eye diagram of PLL output in cscope. thanks.
  3. C

    PLL&Matlab question

    Use "LTIVIEW" of matlab. You will see the step response or impulse response of PLL.
  4. C

    exact differnce between multipliers and fingers

    I recommand the simulation using M-factor size and 1-scaled size. - ex w=2u m=5, w=10u And u will find LOD effect about finger layout effect in BSIM lib. Rgds.
  5. C

    Looking for documents relating to RSDS design

    Re: RSDS RSDS ( Reduced Swing Differential Signal ) LVDS ( Low Vlotage Differential Signal ) or Mini- LVDS There are differents each other, for example swing voltage. LVDS --> 350mV, RSDS --> 200mV adding cable line numbers etc. The National Semiconductor FPD web-page will help u too...
  6. C

    Comparator in Flash ADC

    ChikumaMatsumara It seems it has large current consumption.. regards, eyes146@hotmail.com
  7. C

    What is "kick back noise"?

    calculate kickback voltage The kickback noise is concerned by input driving ability at comparator. If input driving ability is stronger than comparator latch, the kickback noise is not concern about comparator function any more. regards, eyes146@hotmail.com
  8. C

    Any special considerations for designing a comparator?

    Simulation for kickback noise Adding the voltage sources to 10k resistor eyes146@hotmail.com
  9. C

    Frequency Doubler circuit

    digital frequency multiplier circuit I think for Freq. doubler with 50:50 duty cycle ( or 60:40 at least), the best way is pll. for example, u want the output 40MHz, u should make 80MHz VCO output and then divide /2 it for duty cycle. But, u should make just logic and for duty cycle, it is...
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