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Re: layout design
Do u mean to say - what are the layout constraints as u move from 65nm to 45nm ?, if so then
Leakage is a very big issue and u should have methods to reduce the same
shortcut virtuoso
i think ur .cdsinit file is supposed to have shortcut keys assigned to a corresponding task. say c for copy and m for move.
so make sure the .cdsinit file contains these bindkeys.
Hi,
can anyone tell how to do noise anlysis in ADE?
a. what type of voltage source should be at the input? i am giving a freq sweep of .01 to 1M Hz and on the noise summary form integrated freq over 10k to 1M.
b. if we go by the assumption that the ckt is noiseless and all noise is at the...
Thanks MSSN !,
One more clarification needed regarding offset measurement in ADE.
We are simulating a current sense amplifier which has a latch kind of structure at the o/p. how can we measure the offset ? [other than the monte-carlo analysis ?]
Are we supposed to do a dc analysis or the...
Hi,
I am new to the cadence ADE enviornment, Can someone let me know how do we get to know the ' Region of operation' of a particular device.
I was able to punch out the operating conditions of the device and it mentions 1/2/3 as region.
is 1 -cut-off, 2- linear and 3- saturation ???
can...
Hi all,
Can i know the challenges presented in 65nm technology and the layout considerations to be made ?
it would be very helpful if i can get some docs/links abt the same and also the tsmc 65nm drc rule deck.
Thanks,
chippi
hi,
we put via's between two metals (which has some resistance), we add more via's to decrease the resistance ( resistance to the current flow) and thereby have a free flow of current in these metals.
now imagine, if u have two metals say, metal1 and metal2. and u just have a via between them...
Re: Post Layout Simulation
post lyt simulation are also done to see if there are any major timing variations ( rise time, fall time or propogation delays) due to the layout added parasitics, there should be less than 10% deviation, and its always better to do post lyt simulation to validate ur...
layout od
hi,
there is one more layer called OD2 in TSMC, what's the purpose of this layer ?
Also to create a active region (N+ S/D in NMOS), and (P+ S/D in PMOS), what is the need to have a seperate Nimp and OD layer for NMOS and seperate Pimp and OD layer for PMOS ?
Hi LagLead,
Thanks for ur tip, it really helped.
and i need some more info :
i am actually comparing all possible CAP's which can be realised through MOS ( to be used as decoupling-caps)
* NMOS realised as CAP : GATE connected to VDD and S/D/B connected to VSS...
Hi LagLead,
Thanks for ur tip, it really helped.
and i need some more info :
i am actually comparing all possible CAP's which can be realised through MOS ( to be used as decoupling-caps)
* NMOS realised as CAP : GATE connected to VDD and S/D/B connected to VSS...
hi laglead,
Firstly, i wanted to know the region in which the mos'es are operated in that configuration ?, At any point of the time what is the voltage at the gates of the pmos and nmos ?
else it would be really helpful, if u could suggest us any simulation setup which can help us understand...
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