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Recent content by chinnisunny

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    Difference b/w Test chip and normal chip

    Hi Experts, I sort of have a simply rather silly question in my mind. What is the difference between a "test chip" and a normal "chip" Experts please help me clear my doubt. Thanks in advance.
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    Cadence Skill function for changing the layer properties

    Re: Cadence Skill Could you please share the solution that you got so that ppl like me who dont know would be benefitted. Thanks in advance.
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    where do we do scan reordering in the flow ?

    Re: scan reordering All i know is that scan reordering is done inorder to reduce the routing congestion. In the flow this is done after placement and before routing the design.
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    Why do we put Reverse biased diode close to gate which is violating Antenna check ?

    Re: Antenna check We insert reverse bias diode to provide the path to discharge the collected charges,so that the gate wont gets damaged. This is my understanding plz correct me if i am wrong. Thanks.
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    Reg: Timing Verification

    Plz can you send one copy to chinnisunny@yahoo.com.Thanks in advance.
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    LVS without GDS of standard cells

    lvs box option Hi Hussain, When ur doing LVS for top you have the TOP CDL file where inside the TOP CDL file you will INCLUDE all the other CDL files. I guess inside this file you need to specify the list of cells u want Calibre to treat as black boxes.you can do search if you have calibre...
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    What is the diffrence between DRC and DFM ?

    Hi, DRC means Design Rule check(like width of metal,Distance b/w two wires etc) DFM mean Design for manufacturing which means the issues related to Leakage power,Dynamic power Hope this helps.
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    high vt and low vt cells

    disadvantages of low vt cmos device The difference that i know is the amount of doping the diffusion, the difference in the threshold voltage makes them different from eachother. Please correct me if i am wrong. Thanks,
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    Software for doing timing closure

    Re: Timing closure Yes even i have heard about ETS (Encounter Timing System) which is the timing signoff tool from cadence just like Synopsys Primetime.
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    HFN synthesis and CTS

    max_fanout max_cap You mean to say HFNS is for reset and Scan. and CTS is for clock.I think Clock also comes under Hign FanOut Net(HFN). Please clear me i am confused. Thanks, Chinni
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    What is the relation between R, C and delay in wire load model?

    Re: Wire load Model No Probs.you are welcome to ask more q's.
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    What is the relation between R, C and delay in wire load model?

    Re: Wire load Model Hi, R = V / i = (q/C) / (q/t) = t / C Therefore t = RC The product ‘RC’ is called the “TIME CONSTANT” This determines the delay of the cell Hope it helps, Thanks, Chinni.
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    The information about the Flip-Chip

    Re: Flip-Chip Hi all, Here i am attaching a file with flipchip information and its advantages over wirebond,I hope this helps. As per coming to the library for bumps i dont think we need(or get anywhere) any special library for bumps(If doing P&R). Please correct me if i am wrong. Thanks...
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    what is cell delay?and cell delay depends upon what paramets

    Re: what is cell delay?and cell delay depends upon what para Hi, As per i know Total delay or path delay = Cell delay + Net delay “Net Delay” refers to the total time needed to charge or discharge all the parasitics of a given net Total net parasitics are affected by net length...
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    How to import Cadence rule deck format to Synopsys?

    Re: rule deck format Hi, I guess if you are talking about the DRC/LVS rule deck files then the format is the same whether it is synopsys or cadence. Please correct me if i am wrong. Thanks, Chinni.
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