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Hi, All,
I got an issue with timing report by timeDesign in innovus tool as below:
Path 1: VIOLATED Setup Check with Pin u_cortex_a9_mp/u_scu/u_scu_ram/u_scu_ram_
array/u_tag15/CLK
Endpoint: u_cortex_a9_mp/u_scu/u_scu_ram/u_scu_ram_array/u_tag15/CEB (^)
checked with trailing edge of...
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