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TimeDesign in innovus with value 0 of Shift Phase

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chineselboy

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Hi, All,

I got an issue with timing report by timeDesign in innovus tool as below:

issue.JPG


Code dot - [expand]
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Path 1: VIOLATED Setup Check with Pin u_cortex_a9_mp/u_scu/u_scu_ram/u_scu_ram_
array/u_tag15/CLK 
Endpoint:   u_cortex_a9_mp/u_scu/u_scu_ram/u_scu_ram_array/u_tag15/CEB (^) 
checked with trailing edge of 'FCLK_CA9_G1_L1_DIV2'
Beginpoint: se_i                                                       (^) 
triggered by  leading edge of '@'
Path Groups: {default}
Analysis View: scan_ss_m40_3s_cworst_m40
Other End Arrival Time          0.555
- Setup                         0.244
[B][COLOR=#ff0000]+ Phase Shift                   0.000[/COLOR][/B]
- Uncertainty                   0.200
= Required Time                 0.112
- Arrival Time                  0.253
= Slack Time                   -0.141
     Clock Rise Edge                      0.000
     + Input Delay                        0.000
     = Beginpoint Arrival Time            0.000



the line with red light was supposed to clock cycle, right?
How should I set some constraint on innovus for this? Thanks.
 
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ThisIsNotSam

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phase shift means that the path is from a negedge to a posedge, for instance, instead of the normal case where paths start at one phase and end at the same phase (posedge to posedge). phase shift != clock cycle.

also bear in mind that this is not a flop to flop path, it probably is some sort of clock gating path or macro path?!
 

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