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Hi sharankumargoud,
During the synthesis of my verilog file using DC compiler, it created the files .DDC, .SDF, .SDC and .V. The .V file is the one i have imported in the ICCompiler after i have created my MW library....
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Hi Sharankumargoud,
during the synthesis of my...
Hi everyone... i really need help...
i run the ic compiler gui already using icc_shell -gui and have my setup done using the gui also... my search path, link library and target library are setup already and the same is done with my TLU+ files... i have created a Milkyway library as well, with...
Re: the signal reset_ibuf has no load.
Excuse me sir, im kinda confuse... you have posted the site to interface w/ serial but i still dont know how to implement things further... my question is, is there any exercise that i could follow step by step on implementing it... i dont know where to...
Hi, im really new to this project and i dont know where to start. All i know is that i could use the hyperterminal for me to send data towards the FPGA... but i dont know how to do it... also the hardware stuff for the connection between the PC and FPGA... what i want is to make a simple project...
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