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Recent content by chihwt2003

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    Why does PMOS have to be 3x bigger than NMOS in a gate ?

    Transmission gate basic Hi all, Just want to ask why do we need to size Pmos aprrox 3 times bigger than NMOS for a transmission gate? WHat is the effect if both NMOS and PMOS are same size? Thanks. CW
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    Recommendation for op-amp?

    Hi all, Can anyone please give some suggestion on what type of opamp is suitable to be build following these specifications: 1) VCC=3 to 5V 2) Rail to rail input and output stage. D-range is about VCC-0.4V for input and output. 3) THD < 0.1% for 20Hz, 1kHZ and 25kHz. 4.) GBW > 1MHz 5.) Open...
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    How to derive these equations???

    Hi v_c, I've checked the datasheet and the typical values used are shown in the atachment. For calculating the gain they use C1=C2. I think for calculating the Q factor, the value of R3 cannot be ignored since its value is significant compared to R1 and R2. Maybe the Q factor from the datasheet...
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    How to derive these equations???

    Hi v_c, Thanks for the help. Given u 5 points for that :D CW
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    How to derive these equations???

    Hi all, Please have a look at the attached document.I come across this datasheet from Mitsubishi Electric Volume controller. Does anyone knows how to derive those equations? Please help. Thanks Regards, CW
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    Advice about edge-detection circuit

    Re: edge-detection Hi wang1, May I ask how can I clock the D-Flipflop of ur suggested circuit??? May I know are there also any reference material that explain the woking of your circuit? Thanks. CW
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    CMOS Bi-Phase complementary clock

    Hi all, Does anyone knows how to design a CMOS bi-phase complement clock generator which have a minimum delay at the output??? Thanks in advance.
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    How to design a CMOS bi-phase clock generator?

    CMOS bi-phase clock Hi all, Does anyone knows how to design a CMOS bi-phase complement clock generator which have a minimum delay at the output??? Thanks in advance.
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    Mentor Graphics - Simulation problem

    Hi all, Does anyone knows about convergence problem during simulation in Mentor Graphics? Any idea how to solve it?Please help. Thanks. CW
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    How to construct a JK flip-flop using transmission gates or complex gate logic?

    Hi, Does anyone knows how to construct a JK flip-flop using Transmission gates or complex gate logic with a positive edge clock triggered? Thanks in advance.
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    How to output audio signal/data signal via speakers using Matlab?

    Re: Mathlab - Sound Thanks. However, what I want is to output the signal after sampling out a data waveform using simulink, not importing wave file or any other audio file to play.
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    How to output audio signal/data signal via speakers using Matlab?

    Hi, Does anyone knows how to output audio signal (sine wave) or data signal aquired out from a speaker using Mathlab? Thanks
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    How to model ideal switch using ideal dependent sources ?

    Re: Ideal Switch Modelling Thanks for the links. By the way I am using Mentor Graphics for the simulation. Do you know how to create an ideal switch model file so that I can then later use it as a component in the schematic? Thanks in advance.
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    How to model ideal switch using ideal dependent sources ?

    Ideal Switch Modelling Hi All, Do you know how to model ideal switch using ideal dependent sources ? :CCCS :VCVS :CCVS :VCCS Please help.Thanks.
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