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Recent content by Chenxin Jiang

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    Encounter LVS error in Calibre

    Hi there, I was running Calibre LVS check for my design but I encounter some problem. When I run LVS check on module level, which means check each module individually, there is no error. But after I run top level design check, which contains all the submodules, it reports many LVS error in the...
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    Nwell floating when doing ERC check

    Thanks Sam, I have fixed that error. I didn't insert welltap cell on the endcap row, hence they're not connected to the power net.
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    Nwell floating when doing ERC check

    Hi, I was doing LVS check for my backend design. I use tsmc 28nm hpcp library and Innovus+Calibre flow. It tells me that there exits floating n_well in my design and my lvs check doesn't pass. I found that the floating n_wells belong to the endcap along the block boundary inside the block(I...
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    [SOLVED] Power stripe violation near the macro boundary

    Thanks Sam! I have resolved the problem by moving the macros away from the power stripes. Could you give me some general tips on adding power stripes? Now I just assign the width, spacing and #sets of the stripes and I feel I cannot control them well.
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    [SOLVED] Power stripe violation near the macro boundary

    Hi there! I encounter some problem when doing power plan using innovus. After I add power stripes and do sroute to connect the core pins, I found that there are violations at the boundary of the macro. It is caused by the via coincide with the io pin of the macros. Also there are spacing...
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