Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
transceiver design
Hello,
I was wondering how analog intense is the high speed transceiver design. I want to do IC analog circuit design.
I see a job description that says "looking for Analog Design Engineering position to join the High-Speed Transceivers team"
But I have no clue as to what...
I think for a patent infringement (and you should double check this) you'd have to violate all the claims in their patent. And so you have to read thru the boring patent disclosure if you are not sure.
If your design uses all the claims listed in the pipeline AD converter patent, you are...
Match!!!
I dont know what your area constrant is and how crucial the matching is. But here is apossible solution:
D A C A C |A| C A C A D
D D D D D |B| D D D D D
D A C A C |C| C A C A D
D represents dummy and the y-axis of symmetry is where A B C reside (vertically) shown by | |.
There are...
1. When you are doing your literature search before designing, search the uspto and europen patent office (who have websites and search facilities) to make sure what patents are there that are applicable in your area. And, if there are patents, check their expiry dates.
2. Maintain a record book...
The base of Q5 and Q6 are floating. That is there is no current path to go to base. Since these are current driven devices the base cannot be floating when the operate. Put a voltage source from the base of Q6 to gnd and likewise for Q5. Or, connect gnd to the negative terminal of Q6. That way...
Gm/Id methodology
In my opinion we have to first understand that there is no abrupt transition between weak inversion and moderate inversion, and modeterate inverstion and strong inversion, and strong inverstion and velocity saturation.
Having said that if you have decided that you need a...
how to calculate the maximum voltage gain
1. To your first question about sizing M7 and M8:
It is not difficult at all. M7 and the way you are biasing the gate of M7 (popularly done with just two PMOS diodes to Vdd) together with the PMOS output transistor forms a translinear loop. Therefore...
how to calculate voltage gain
the NMOS PMOS combination between A and B seems to like a Class AB control circuit. Also, there is an AC short between point A and B. You can convince yourself by doing proper analysis. Therefore, you can calculate the voltage gain of the amp as you would do...
This will definitely help you as far as ESD. But it depends on the value of the resistor. For MM ESD it probably helps the NMOS if the resistor is of small value. For HBM ESD, I think this has to be like 1kOhm for it to significantly help ESD.
ESD help
Chang,
I will try my best to you help you. I am writing quite a few questions. I dont expect you to answer them all to me. This is just to see if you have thought about all these ideas.
Questions/Comments:
1. Is GNDA and GNDD tied together when you do the ESD testing? Is it tied...
diode connected load inverter
1. firstly for a current souce you want a very high output impedance, which is not possible with a diode connected device as luckypearl25 has mentioned.
2. Voltage swing is better for a regular transistor (say NMOS) because the drain can go Vtn below the gate and...
question/
Without looking at a specific op-amp, these are my suggestions/comments:
Since Power Supply Rejection Ratio is the Gain from the power supply to the output rejected by the open loop gain of the amplifier:
1. Make sure you have a high open loop gain
2. Power supply noise coupling to...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
