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There is no such thing as zero BER in a realisable system. The Shannon Channel limit theorem states every channel has a limit. I am not sure why you saw 'zero BER'. Possibly your noise is so low that your channel is very good and BER looks close to zero? This already seems like a problem with...
All fixed.
I found I had accidently introduced a new, blank UCF into my project at some point, which was associated with the top level module. The resource placement was therefore arbitrarily chosen it seems. The UCF file I posted and was editing was totally irrelevant it seems.
Big thanks...
Hi mrflibble,
You are correct, that would be a big fat error. At the time of writing my last I was making lots of attempts with slight variations of my code, and the one I posted happened to be syntactically broken. However, I fixed that error with no improvement in my result. I like the...
Are you planning on (a) implementing an error correcting scheme, or (b) do you just want to try for the best unencoded transmission? If (a) then try viterbi, turbo or low density parity codes. If (b) then either slow the data rate, increase the signal power, or lower the awgn level.
Interleaving is basically taking a block of samples from your signal and shuffling (interleaving) them around before sending them. This is so that if a short 'burst' interferer causes errors in a number of bits in the channel, the errors affect bits that were not actually next to one another...
Hi Barry,
Yes, I have used this UCF file for the previous experiment (almost identical). I have triple checked the resource references (e.g. SW0 = L13) and they are correct.
I even tried setting
assign indicator = 1;
in my verilog file just to make one of the LEDs come on. Still no luck.
Hi, This is my first post!
I am really new to the world of FPGA and am trying to educate myself from a FPGA prototyping textbook, but came unstuck with one of the early experiments.
The Verilog program is a 2-to-4 binary decoder. The UCF is below. I added the "indicator" signal because I was...
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