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Recent content by calliste

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    How to convert a layout netlist form Calibre to a netlist readable by cadence ???

    Hi all, I want to do an LVS with Diva (cadence). For the layout I have a layout netlist given by Calibre netlist extraction through nmLVS. But this netlist is not accepted/readable by diva LVS. There is a way to convert this layout netlist to be used with Cadence. Any Idea is welcome! Best...
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    help for SS corner simulation with spectre Cadence

    Thanks JoannesPaulus, I checked my bias circuits and the problem came from the bias of the cascode that was to low in SS corner, causing the input transistor to be out of saturation. Best regards!!
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    help for SS corner simulation with spectre Cadence

    Hi all, I'm designing a telescopic cascode amplifier for a charge preamplifier. It works very for typical paremeter and also for FF FS FS corner simulation. However it works abnomally with SS corner simulation. Does anyone have an idea about what to do to have my circuit works in all corner...
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    Please looking for this TSMC Document T-018-LO-DR-001-C2

    t-018-lo-dr-001 I everybody!! Please, Do anyone have this document T-018-LO-DR-001-C2??!! it's a document from TSMC that explain how to autofill a layout in TSMC CMOSP18 DK. Thanks!!!
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    Help me solve some LVS matching errors

    LVS matching error yes I checked the rule file permuteDEvice statement are present and it's nfet in both netlist and DivaLVS.rul file. also m factor is present in the schematic netlist
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    Help me solve some LVS matching errors

    Re: LVS matching error it's TSMC CMOSP18 PDK. Could you more explain PMOS[1:10] syntax.?? Thanks
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    LVS issue with extracting info about multiple gate transistors from the layout

    Re: LVS issue hi Teddy!! thanks for your response. by "bus" representation PMOS1[1:6] do you mean to place in the schematic 6 transistors in parallel? for a very large circuit, this is not very convenient. Doyou know another way more efficient??
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    LVS issue with extracting info about multiple gate transistors from the layout

    Re: LVS issue hi everybody!! I'm faced to the same problem with diva about the handling of M factor do anybody know finally howw to resolve this? Thanks
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    Help me solve some LVS matching errors

    LVS matching error Hi could U please send me the DivaLVS.rul file you used (Maybe it's my rule file which is wrong!) thks!!
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    Help me solve some LVS matching errors

    LVS matching error yes I have.
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    Help me solve some LVS matching errors

    Hi everybody I'm using Diva from Cadence to run LVS. I get many nets and devices mismatch when running an LVS. This is due to M factor of mos transistor, and also because I draw my MOS transistors in Layout using multifingered design. I thought LVS didn't recognize parallel device, but I...
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    LVS problem about multifingered mos

    hi onlymusic16 and sandeep_torgal. where do I need to set parallel option. I didn't find the right file!!! thanks
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    Problem with streaming out CDL in Dracula LVS

    Re: about CDL? How did you make your mosfet Cdl export?? Did You get problems like error: Netlister: unable to descend into any of the views defined in the view list :' auCdl schematic'?? Thanks
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    What is the role of the active zone layer in CMOS processes?

    Re: active zone that what I think too, but why is it necessary to put an active layer when we connect Metal_1 with Nplus or Pplus Layer???
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    What is the role of the active zone layer in CMOS processes?

    Hi, I would like to know what is the role of the active zone Layer in CMOS processes!! thanks
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