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This is why I provided the schematic for LTspice, so anyone can see and run the simulation, thus having all the answers beforehand, like the already present dead-time (also mentioned in #4). This way, IMHO, all the answers will be based on facts rather than theory and assumptions.
Yes, but Coss usually drops with Vds. Unfortunately, the datasheet for this ZVN0545G in particular, doesn't show any graphs, in fact, it seems too few from DiodesInc have. Still, the results seem to be good now, I'm getting no cross-conduction and ~25mW/FET, instead of the 400mW+ (in the good...
I, for one, prefer NXP, or Fairchild, but they don't seem to have what I need now. I went to DiodesInc and they have a nice list of models, but there aren't too many high-voltage high-speed NMOS. There are a few, though, and their models seem reliable enough, for example, ZVN0545G has Rds=50...
True, but the models in LTspice are limited. Besides, I also omitted the effect of the large filtering inductance (30mH), V(x) wouldn't go low with Vgs.
Do you, by any chance, know of a high-voltage, high(er)-speed MOSFET model for SPICE? It doesn't have to be high-current since I'd be dealing...
Using the ST part was because that's what LTspice has in its default list and, while I agree that using a better part with lower charge and/or Rds would give better results (I couldn't find SPICE models for the A&O MOS you gave), the results are the same.
For example, among the things I have...
Hello
I attached an LTspice schematic, a very simplified version of a MOSFET half-bridge driven by a push-pull isolated signal transformer. The FETs are cross-conducting, but their gate pulses are not overlapped. If I am getting things wrong, can someone please show me the error, why are they...
In the meantime someone gave me the answer: the first formula, γi=(σi−1)/(σi+1) is correct, but the determination of the poles in the s-domain is wrong, in that all the four parameters, As, Ap, ωs and ωp, need to be specified such that the resulting N is closest to integer, without using ceil()...
Hello
I am trying to model a bireciprocal Cauer filter in LTspice but I don't get the expected results. More precisely, using
γ=(re(s)−1)/(re(s)+1)
where re(s) is the realpart of the pole, gives this result:
**broken link removed**
Among the few references I have, one that gives a numerical...
I managed to solve it by print-screen-ing the images from the Burrus' collection and mine, from wxMaxima, and then comparing them with the Gimp. In his graphs he used the step trace to match the 0.5 value, not tas the original one, which was what confused me. It seems I'm doing alright as I did...
Hello
I tried implementing this in LTspice, but I don't seem to get good results. I am using for this the IDCT/IDST, and here are the results for wc=pi/2, 21st order, between a normal un-windowed sinc filter, V(fir), and a FS, V(x):
and the coefficients:
For this example in particular, I...
Tahmid,
I agree with what you said, but the OP said 12V input, therefore not a problem. As for the Rds_on, that's for the catalog to provide and user to choose from, while the high-frequency and high-currents could be a problem, but the OP said he'd drive the switch directly from a uC, so my...
Why complicate things with IRs instead of using a simple 2N2222 (for example) as a level shifter for a PMOS? Well, it's your design, so your choice.
Good luck,
Vlad
Hello anarion
Driving the NMOS' gate will require a voltage swing between <Vout or 0V ... Vout+Vgth> at its minimum, therefore if you have 5V output and its threshold voltage is 2V, you will need a bare minimum of 5+2=7V. This means that directly driving it from the uC will not work. You could...
This is either a curse, or luck, and it's not the first time... After posting I realized that, the way I am using the transfer function is derived from the state-space direct formula which made it possible to find the poles (,zeroes) and use their wp=1 normalized value, resulting in (using idt()...
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