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Feeds behavior(crisscross),number of feeds matter and that also comes under IO pin density
Up to what extent over macros blockages are present and how many dedicated metal layers are available for signal routing apart power routing...
pre timing need to get clear without any violation at logical synthesis stage. Then we can continue with that netlist at physical design stage.
If pre timing itself not clean we wont meet timing at the physical design stage even by doing repeated floorplan experiments.
Thanks oratie..
I checked manually by changing output load there is no change in the setup time requirement.It remained same.yeah no dependency on output load.
In general all these data provide by the specification team. Based on this front end synthesis team develop constraints. And back end designers run with those constraints and provide feed back to them. It's a continuous loop. Definitely constraints defining is not a single shot.
For...
vijay,
Pls refer to synopsis design constraints and timing constraints user guide for more info... It explains each individual question of yours
But to answer your question how to constrain design below mentioned are some set of commands familiarly used. Even I missed out some commands but as...
Hello All,
Can anybody explains on what parameters library setup time and library hold time requirement depends/ characterize ?
In my case I pretty much observed a change in setup time requirement for a ram especially by adding buffer and without that..
Here is an example
By default:
library...
What's your target limit for hold ?. 14% utilization jump is pretty huge number. I thought you are over constraining your hold limit...
Are you allowing IO optimization at your block level? Do you keep tighter constraints for IO's? Because seeing 8% utilization growth at incremental prects...
Sunidrak,
Gud to start with programming languages C,C++ and scripting languages perl,TCl and Cshell. Which will help you comfortable in the work environment.
For verilog Hardware Description Language refer samir palnithkar. For backend implementation start with "physical Design Essentials" ...
I completely agree with jeet_asic statement... setup and hold violation could occur for the same start and endpoints including same data levels at different process corners.
What ever morris_mano explained is for same start and endpoint but traversing through different logic levels.
kumar,
It's not necessary to add the delay or normal(ie.. utilization not an issue) buffer at the endpoint. we can do that (adding at endpoint) if there is a margin otherwise we look for diverging point we keep buffer by checking required margin there are not.
But I dont understand "hold delay...
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