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Recent content by bronzefury

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    PLease Vote: Electronics Engineer Vs Computer Engineer

    I'm an EE designing ASICs. I enjoy it very much. I also find learning about and writing software enjoyable. So, from the view of "Do-what-you-like", I could've gone either way. That said, it appears to me that software route has more jobs available than hardware - if jobs are what you are...
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    startup or BIG Company

    If you are young, energetic, ready to learn alot, and don't have any major responsibilities (like wife and children),.. I would recommend going to a startup. You can always get a job at a big company later on.
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    Which reset methodology consumes more power?

    Do you happen to have any numbers showing power consumption for different types of FFs, sync and async?
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    Which reset methodology consumes more power?

    I'm not exactly sure yet. Power Compiler basically calculates this based on the ASIC vendor's library.
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    Which reset methodology consumes more power?

    28.7% (in mW) more dynamic power consumed by Synchronous Reset design versus Asynchronous Reset design. 18% (in uW), more leakage power consumed by Asynchronous Reset design. These are the results when running report_power from Synopsys Design Compiler Asynchronous Reset Design, 90 nm, 200+...
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    Which reset methodology consumes more power?

    Hi, Well, I did an experiment on a 180,000 gate module - one with asychronous reset, the other with synchronous reset. Synthesized them both and ran dc_shell command called report_power. In a 90 nm process, the results showed that synchronous consumed 30% more dynamic power (in the mW range)...
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    Which reset methodology consumes more power?

    g90ld g90fd g90d Hi, Which reset methodology consumes more power, asynchronous reset or synchronous reset? Thanks, bronzefury
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    What is the internal power in power consumption?

    Re: internal power problem Hi sishir, What do you mean by "split-memory words"? How does this reduce power consumption? Thnx, bronzefury
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    How to change clock frequency?

    You'll need two input clocks, 25 MHz and 66 MHz. Out of 25 MHz, multiply by 5 using a PLL
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    Help me generate waveforms for a given clock

    Re: clock design novicelsi, is there a reason why duty cycle has to be 10/50? also, why is flop count an issue? are you running out of room in your chip?
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    Help me generate waveforms for a given clock

    Re: clock design Hi, Would this help? Please see attached. bronze
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    What are the functions of debussy?

    Re: debussy! Hi, Debussy can also help you trace a waveform signal to source code. As you view source code, you can figure out which module is driving a signal and it can show you which is receiving a signal. In addition, you can see the values each wire or register in your source code are...
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    The results of using multiple always blocks for signals?

    Re: RTL question If that combo block contains one state machine then I don't see a problem either. But if you are mixing state machines within one combo block, then you've got a problem (or rather, a major headache).
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    Help me generate waveforms for a given clock

    Re: clock design Does your design only use flops that are triggered by rising-edge clocks?
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    Estimate gate count in Verilog?

    Hi, If you happen to have Synopsys Design Compiler in-house, this might help. This example uses a 130 nm library from LSI Logic. So, yes, the library and technology matters. The example below is if Synopsys reports cell units - which it did for 130 nm LSI library. Gate Count estimation...

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