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Recent content by bright8848

  1. B

    why Downsizing of cell is done?

    Maybe there is another reason that decreasing area of chip.
  2. B

    How to design AND Gate using one pMOS and one nMOS

    And then A and B are all changed to 1, output will be 1? even if it's connected to a pulldown load?
  3. B

    loading SDF during simulation

    Yes, I thik it is OK.
  4. B

    Circuit to detect clock with a little higher frequency

    This method will be OK when simulation. But If it will be realized to a curcuit, maybe one issues will happen. Which clock domain the gate signal is drived in? If in A clock domain, it will be sync two beats to control B clock domain, and then the counter accuracy will be influenced.
  5. B

    incomplete sensitivity list in always block

    I think simulator just excutes the RTL code and knows nothing about the structure of curcuit. It's sure that when only the missed signal toggles, always block won't be triggered.
  6. B

    incomplete sensitivity list in always block

    Will it report error when synthesis?
  7. B

    source and generated clock in SDC for synthesis

    I don't think it is necessary. The delay though paths is fixed in the same corner no matter clock toggles or not.
  8. B

    AND gate for clock gating

    Can you give some detail about this issue?
  9. B

    AND gate for clock gating

    If the clock enable signal de-assert when clock signal is high, a glitch will apear.
  10. B

    What is the synthesis of this rtl?

    Re: synthesis of this rtl Hi Sun_ray, would you please give me a link for this document? Thank you~
  11. B

    How the task is being called

    Assumpt the instance name of the module including task is DUT1, and the task name is "test_tsk", you can use "higher_hierarchy".DUT1.test_tsk to call this task. If there's assignment in the task, the calling only can change signal define in DUT1. Hope it's helpful.
  12. B

    What is the synthesis of this rtl?

    Re: synthesis of this rtl I have the same puzzle. By the way, what's difference between block assignment and non-block assignment in combin logic? Thank you very much~
  13. B

    Retention Flop basics

    I think cross-coupled inverter seems like a simple latch, retention flop is special flop for low power design.
  14. B

    Issue about HPET FSB Interrupt

    The SPEC. says that To use FSB Interrupt mode, the interrupt must be configured to edge-triggered mode. Why? considering we don't care about interrupt pin in this mode. Thank you!
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