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So if there are four integer point : point0 point1 point2 and point3
Set downsampling point at the fractional point location 0.1. The value of point 0.1 could be calculated using Lagrange interpolation.
In matlab it’s very easy to calculate the downsampling location point...
Re: how to update flash with user logic?
it's xilinx 7 serise, and CCLK is a dedicated pin. So I assume it could only be used via primitive, but not directly.
I'm having trouble uploading picture..the schematic is exactly the same as ug470, p51, figure2-12, the Master SPI mode...
I want to download bit to FLASH, not by JTAG, but by user logic. I now have one possible idea in mind:
Because CCLK is a dedicated pin, user logic cannot use it(I know by primitive it can still be used, but not now). Instead use a common-purpose IO, define it as a SPI_CLK output to FLASH.
In...
Thank you. I followed your advice and it works. It's better to use ^ and & than "*" "+" in Gf(2).
the code I firstly post is wrong:
b[i] = A[i][0] * x[0] + A[i][1]*x[1] + .... + A[i][191]*x[191];
I assumed that, since A is a fixed matrix of elements of either 0 or 1, even though I...
generate
for(i=0;i<192;i=i+1)
b[i] = A[i][0] * x[0] + A[i][1]*x[1] + .... + A[i][191]*x[191];
endgenerate
I think this is the best I could do...at least 192 items should be typed. The one-line matlab-like b(i) = b(i) + A(m,n)*x(n) is beyond my skills.
1. it is for FPGA
2. verilog
4. the diagram is simple, but requires lots of typing which I'm trying to avoid
3. I want to avoid typing the following code:
b(0) = A(0,0) * x(0) + A(0,1) * x(1) + ... + A(n-1,n-1) * x(n-1);
b(1) = A(1,0) * x(0) + A(1,1) * x(1) + ... + A(1 ,n-1) * x(n-1);
...
b(k)...
A*x = b, in which A is matrix, x and b are column vectors. Each element in A or x or b are all 1-bit width.
The * and + are all mod 2!!
A is like
1 1 0 0 0 0 ... 1 0
1 0 0 0 0 0 ... 0 0
.
.
.
1 1 1 1 0 0 ... 1 1
so Ax=b could be:
b(1) = x(1) + x(2) + ... + x(n-2) // "+" is mod(2)
b(2)...
How to use simulink with modelsim, when there's ipcore involved?
I have no problem running simulink to invoke modelsim, when there's plain verilog files.
But when there're Ip cores, the process always fails.
I'm not using the Dspbuilder or System generator. Just want to use simulink to...
I'm trying to use Xilinx Srio Ipcore and could generate the example design( generated automatically by Vivado) which could be simulated properly. However it only simulates properly when I change nothing in the ipcore GUI.
The default transfer frequency is 5Gbaud. I will need to use 3.125Gbaud ...
incoming sine wave is already digitized. To track it, I intend to use a all-digital PLL, which consists of a phase comparator(a multiplier), a loop filter and a NCO.
Earlier I was confused with the concept "equal steps", or "fixed phase increment". Now I see it's not necessarily a fixed phase...
I'm trying to implement a digital PLL to track a certain frequency. And I need to implement a NCO in it.
I learned there're 2 ways to do that.
1. Using IPcore to generate a NCO
or
2. Using a counter as phase accumulator(with fixed step size increment) and a LUT as sine table.
The above 2...
OFDM symbols use cyclic prefix and CP could be used to calculate the start of OFDM symbols.
It's usually by correlation. I've done the simulations, but the resultant estimated OFDM starting point is not stable. They vary within a range of [-20,20].
I know these difference could be eliminated...
just out of curiosity, how do you guys do math in FPGA?
Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add.
As to other operations such as cordic...IPcore is my first choice...
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