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So basically , lets just say there is a external clock generated via crystal oscillator which is also used by the FPGA chip as reference. Now is it possible to implement a monitoring logic ,in the same FPGA, to detect the failure of the external clock from crystal oscillator?
thank you for your reply. I am new to this. I am designing the filter for 50 Khz and 39 Khz separately. So what should be the timing window period be ? Should it be greater than 1/ (50 k) and 1/ 39k respectively or something else?
I was thinking to use a matched filter with peak finder. What do...
I want to write a code for a system which detects the absence of AC signal ,received after the digital filter (sampled @ 200khz).
My ideas
1. level detector - If level is zero - no ac signal.(I liked it the most but struggling to come up with logic:bang:)
2. Continuously measure frequency of...
Hi,
It is actually a working circuit. I made a typo on the label of resistor 10k (labelled as 10 pF). This is the circuit used in field (as is) and my intention is to implement the whole thing in FPGA (a Digital filter).
Please find the circuit attached. I used the below link for reference but I got an error saying the the block in empty and hence no output could be plotted. I am trying to capture a step response and then use it to calculate transfer function for the same.
If any one is able to produce the the...
I want to implement a digital filter and tuned amplifier for (39 KHz and 50 kHz) in DSP. Currently the whole implementation of filtering transients and noise and tuned amplifier is in Analog and I would like to implement everything using DSP with excellent noise immunity.
As the circuit gets...
Please find the attached simulation and required verilog files (notepad).
If you see the simulation ,you would notice 00x values as output and it is in red. It is expected that the output is 3 bit number instead of 00x. I am unable to rectify the problem. (Modelsim starter edition)
I have tried...
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