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when designing LC-VCO, the low-Q of on-chip inductor is often the bottleneck of high performance. So I want to try off-chip inductor (other components are all inside the chip, including varactor). Who has information about designing LC-VCO with off-chip inductor?
If you know the spectrum of phase noise, you can get the rms jitter by integration. In the website of ADI, you can find some papers about how to integrate, e.x. AN-756.
The top 4 foundry is TSMC, UMC, Chartered, and SMIC. I want to know about the difference of their process, so that I can the process that fit my projects best.
Any comments are welcome, especially about the 0.18um/0.13um Mixed-signal/RF CMOS process.
Now the product of PLL with spread spectrum can be found in the market. But I cannot find the materials about how to make spectrum spread by searching in google.
I only get two papers in the IEEE website. Where can find more materials?
high pass filter 0.05hz
just a thought for your information:
change the input signal to a digital signal, use a digital filter to realize your requirement of 0.05Hz cut-off LPF, then change the result to analog signal and output
the following circuit is used as 5V tolerance input circuit for a 3.3V CMOS process.
all the MOSs are 3.3V devices.
as I know, the break-down voltage of the PN between the drain and the substract of N3 is not higher than the break-down voltage of the gate of N2. So I think that using N3 to...
Check the node of 1:noxref_2641. It is not difficult to confirm whether there is dc path to ground from this node.
Comparing to pre-sim, there are many more parasitic capacitors in netlist. It is also common that some new nodes appear and may be floating.
it is OK to design 3mA current mirror by using pmos.
because the current is a little high, choose the suitable w/l of the transistors. also, check the number of contact, width of metal for current density.
BTW, are the transistors connected to PAD? if yes, follow the ESD rule.
Which of following matchs best to a singal NPN transistor with the relationship of 1:N? And which one is the worst?
1. n NPN transistors. In layout, the n transistors can be put together and beside the signal transistor, but cannot put around the singal one.
2. a NPN transistor, with n...
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