puzzle about 5V tolerance of 3.3V CMOS

[borislee]

the following circuit is used as 5V tolerance input circuit for a 3.3V CMOS process.
all the MOSs are 3.3V devices.

as I know, the break-down voltage of the PN between the drain and the substract of N3 is not higher than the break-down voltage of the gate of N2. So I think that using N3 to tolerance 5V is not reasonable.
who can tell me why I am wrong.

BTW, when the PAD is 5V, the ESD device of P1 will have current so it is not good here. Am I right? What is the better circuit for ESD?

 

[mists]

the p1 maybe should floating well.

 

[borislee]

What is the help that P1's well is floating?

 

[fendy]

Maybe you can use this schematic.
Wish help you.