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Recent content by borabilgic

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    Implementing MOSCAP in FPGA (or another digital IC)

    It seems transistor level arrangement is impossible?
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    Implementing MOSCAP in FPGA (or another digital IC)

    Hi, Can I implement MOSCAP in an FPGA? I mean can I connect drain and source of a transistor to gnd and gate to another node? It can be another device other than FPGA. Thank you.
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    Supply Voltage Glitch Simulation

    Hi Dick, What is a stiff pulsed source? 1611822184 Hi Dana, I could not get what you ment above. Can you explain a little more? Thank you. 1611822420 I just want to apply a fast changing VDD to a chip (CPU, MCU, FPGA etc.). I just want to know whether it is possible or not? I mean the...
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    Supply Voltage Glitch Simulation

    Hi, I want to simulate VDD glitch. For example I want to raise 1.2V VDD to 4-5 Volts for tens of microseconds and lower back to 1.2V. Suppose I have a high rise and fall time pulse generator (200-500 picoseconds). My concern is that some digital ICs (like CPUs) have some capacitors on them to...
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    MOS Capacitor or a mosfet used as a cap (D-S-B connected to gnd)

    Shoul I tie D and S to ground while building a cap from mosfet? or just bulk connection to gnd is enough?
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    MOS Capacitor or a mosfet used as a cap (D-S-B connected to gnd)

    Hi, in Cadence Spectre simulations should I use a MOS cap instance or a mosfet (D-S-B connected to gnd) to simulate a real life MOS-cap? I tried both of them and they gave different results i.e. MOS-cap instance charges to a higher voltage.
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    Fully diff.amp. without a CMFB

    Hi, can I use the 5-T OTA as a FDA without a CMFB? Does it amplify the input diff. signal? Thank you.
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    65nm process voltage limits

    Sorry I forgot to write pulses for a duration of 1-2 us for testing puposes.
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    65nm process voltage limits

    Hi Dick, Can I apply 3.2V pulses like 1-2ns period(%50 duty cycle)?
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    65nm process voltage limits

    Hi, I could not find the voltage handling limits of 65nm process mosfets. How high VDD can I apply to a 65nm chip and for how long? Thank you.

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