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Re: fpga dual edge ff
Hi.
I used a flag:
variable ClkFlag : std_logic := '0';
My process only includes the clock in its sensitivity list:
process (CLK)
Then, everytime the process is run the flag is toggled:
ClkFlag := not ClkFlag;
The code for rising and falling is selected according to...
We are running a simulation to model transmission through an odd shaped object that we drew in HFSS. We want to put a square wave port on a rounded side of it but can't figure out how do that. Since that failed we put a wave port on one end of the object. The port crosses over multiple objects...
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