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Hello All,
Can some one please help me with this issue.
I have 3 different projects A1, A2, A3 and i am using ifdefs. Can someone tell me a way to avoid such scenario
ifdef A1
<code1>
elsif A2
<code2>
elseif A3
<code3>
endif
code1 and code2 are same, i dont want to use ifndef . So can...
In one of my projects
I have got timing violations for a same register at different times. I wanted to know if though the timing violations are at different times, fixing one would fix the other violation at different time also right?
Hi,
I have checked opencores.org. I have found some interesting projects over there. But I don't think they can be used as a course project. Can some one help me out with few more ideas.
Thank you
asic projects
Hi,
The project must be a course project. It must take 8 to 10 weeks to complete the project.
It would be great if the project idea can be useful for real time applications.
Thank you
asic projects
Hi All,
I need to design a project spec for a course. The course needs a design project which requires verilog. The verilog code is to be synthesized using cadence. Can some one suggest me good projects or some ideas on which I can design the spec on.
Thank you
programs used for drawing circuits
I am sure my reply to this post is wierd, since you are talking about linux. Use Microsoft visio for drawing circuits, its really good. I used it for my projects and it helped me a lot.
I think burst size four is common. Intel Pentiums II and III had cache blocks of length 32 bytes. Since the system (memory) bus is 8 bytes, a burst of 4 yields 4x8=32 bytes, exactly enough to fill a cache block.
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