Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Binome

  1. B

    testing a variable-length value

    The last solution is really simple, I should have thought of it! Thank you.
  2. B

    synchronisation question

    I had corrected everything with what you all thought about and it's working perfectly. I thank you all for your advice.
  3. B

    testing a variable-length value

    Hi, I have a variable-length (depending on a generic value) word and I'd like to test whether it's null or not. Say I have d : std_logic_vector(g_length-1 downto 0) and q : std_logic that should be '0' when d="0...0" and '1' otherwise. How could that be written? Thanks.
  4. B

    synchronisation question

    Thank you. I can't post all the code because of my company privacy policy but I rewrote the process (that was indeed badly written) trying to be careful. It's like that: out_process: process(rst_n, r_hash_done, s_hash, clk) begin if rst_n = '0' then n <= 1; tree_end <= '0'...
  5. B

    synchronisation question

    Hi, I've got a strange behaviour when simulating a design. Here is a part of my design: out_process: process(rst_n, r_hash_done, s_hash, clk) begin if rst_n = '0' then n <= 1; tree_end <= '0'; out_ok <= '0'; elsif r_hash_done(0) = '1' then tree_end <= '1'...
  6. B

    array type range constraint

    Thank you. Making the ind variable an integer solved the problem.
  7. B

    array type range constraint

    Hi, here's a part of my code: wit_process: process(rst_n, s_done) variable wit_addr : std_logic_vector(7 downto 0) := (others => '0'); variable ind : unsigned range 0 to 7 := 0; begin if rst_n = '0' then wit <= (others => (others => '0')); s_wit_addr <= (others =>...
  8. B

    bitwise function description

    So tell me. What should I write for my function to be correct and usable as an instant transformation of any std_logic_vector input (as any logic or arithmetic function)?
  9. B

    bitwise function description

    I thank you but I don't understand everything: For now tmp is (a'range). Is it different from making it (a'length-1 downto 0)? (The simulation result is the same). Then I got a "wait" statement at the end of the process. Is it different from a "wait for" one? Finally I don't understand the...
  10. B

    bitwise function description

    Hi, I have an input std_logic_vector a. Then I want an output one named r defined (depending on an integer n) as: r(a'length-1)...r(a'length-n)='0' r(a'length-1-n)...r(1)=a(a'length-1)...a(n+1) r(0)=not(a(n)) I've defined a simple function in a package as: function wit_addr(a ...
  11. B

    A pseudo-random number generator

    I'll see on the used board if something could be this non-zero value. Thank you.
  12. B

    A pseudo-random number generator

    OK but the FPGA can not be separated from the CPU as a standalone component.
  13. B

    A pseudo-random number generator

    Hi, I'd like to generate pseudo-random numbers in my synthesizable VHDL design. I've found this code : https://github.com/jorisvr/vhdl_prng/blob/master/rtl/rng_xoroshiro128plus.vhdl and it looks great but the seed is stuck to zero in the top-level component. I would like the seed to be...
  14. B

    Questasim optimization

    It's OK for the synthesis with ISE. The pin is available.
  15. B

    Questasim optimization

    I know that but it is an output port so I don't understand why Questa is considering it as not useful. I won't disable the optimization for a specific signal because I'm using a GUI version on Windows so I'll use the general "no optimization" option. And I'll try a synthesis to look at this...
See more

Part and Inventory Search

Back
Top