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Recent content by Bin_Wang

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    photodetector amplifier - help needed

    Re: photodetector amplifier Could you paste your circuit and simulation result ,so we can help you to analysis the problem . BTW, What is your photodetector output signal ? Current or Voltage? What is the relation between the Output and Input Photo Signal?
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    How to reduce PLL Noise due to buffer

    First, what noise come from the buffer ? Device noise or 1/f or other? Second , you can try according dick_freebird and erikl suggestion , third, I think you can use differential to sinle buffer such as comparator as the first buffer , remember , the VCO power supply and comparator power supply...
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    How to convert cdl to schematic?

    I you want heriraical level ,I think you should have the bottom schematic and symble at first ,so you can convert the cdl to schematic . Remmeber ,you should delete the subcircuit nelist, and moidify the reference library just as convert verilog to schematic? Hopw it help you , and you can have...
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    How to convert cdl to schematic?

    You can use the import cdl option in ICFB but you should modify the cdl netlist , MOSFT should be modify the subcircuit format .
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    I5141 simulation states problem

    I use IC5141 to simulate the circuit ,but I can not load the simulation setup which I have saved, such as analysis condition setup etc.... Could Someone have solution to this problem...
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    Capless LDO design- experience sharing and papers needed

    robert milliken capless ldo Could you descsibe What do you want in detail. And what does the capless LDO mean?
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    PLL simulink model with every block in circuit expressing?

    You can make PFD by dual DFF so that you could input Pulse signal
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    Can any one give more details about via

    You should place two via as minumal to link the two layers ,because of the manufacture yield. So you need to modify the LEF for digital PR
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    are these layouts manufacturable?

    DRC only check the violation for manufatured, they do not consider the parasitics, if you want performance and high yield , you should modified the layout
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    Need TSMC 0.18um design rules

    Re: Help! I think you can downlaod it from MOSIS
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    How to simulater Oscillator

    I have been design a Oscillator for 32.768K, and when I simulate the ciruit ,the oscillator can work ,but when the simulate time is long ,such as 500ms and more the amplitude will decrease from 3.3V to zero(the power supply is 3.3V), could some one give me advice ,thanks
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    What are the popular and effective matching methods ?

    Re: matching methos? I think you are right , and the matching not only in layout ,but also in circuit design. The TI high performance product has its own process surpport such as triming ,with this tech, you can got very high precision reference , this in only one example, and some special...
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    The difference between N substrate and P substrate

    I hope someone can give some information about N substrate and P substrate process. I found a dual -slope adc design ,which used N substrate process and I do not know the reason.thanks
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    Comparator used to compare (v2-v1) and Ref

    I have met the problem when design the differential receiver used in USB 1.1 Transceiver,according USB 1.1 spec, the differential sensitive is 200mV ,and Common mode range is 0.8 to 2.5V (include dierential range). So the comparator is needed to compare the (v2-v1) and 200mV, I used the two...
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    How to measue a SC circuit noise using Hspice?

    Hspice can not simulate the noise of SC,because the noise parameter can calculate during the AC analysis, so the Spectre RF is recommanded. PSS , pnoise and PAC is used to simulate the period ac signal such as the SC filter circuit.

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