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how can simulate settling time
Slew rate is nonlinear,usally occure when large signal.Settleing time is linear,OP is linear when input is small signal.
Q1: Anyway,the cmfb loop must stable whatever frequency you are interested in.
Q2: large sin signal has high frequency component because it varies faster than small signal: v(t)=A*sinwt, dv(t)/dt=A*coswt, max(dv(t)/dt)=A so oscillator take place when you add large signal
Q3,you can decrease...
xilinx sigma delta
To design SDM:
1,understand the principle of SDM
2,determine the architecture of SDM according to the spec.
3,behavior modeling scale factor refering to the stablity.
4,behavior modeling the nonideal factor ,such as the cap noise vs. SNR,
slew rate and settling time of...
You must understand the factor affecting THD. Any nonlinearity can contribute to THD. For example, The amplifier need enough gain and bandwidth to get good linearity. You can use matlab model to estimate the performance of filter before design.
Re: What is the most commonly used rail-to-rail OP structure
The configuration proposed by DZC can be used as fully differential architecture.
only else add a class ab control loop and cmfb circuit.
You can reference the book "Design of low-voltage,low power operational amplifier cells" by Ron...
Re: How to bias a OP??
You can bias the cascode transistor by a diode which has a 1/4~1/7 W/L of the current source transistor. 1/4~1/7 W/L determine the output swing.
I think:
1,the gate of M21 should be connected to M17 to reduce a zero.
2,you should add some control circuit to control quiescent current.
3,you should check phase margin at different output level including quiescent point.
good luck!
Re: audio amplifer
To reduce distortion of class AB amplifier:
1,try to achieve high small signal openloop gain and wide bandwidth.
2,try to increase output MOS size to get enough driver ability .
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