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Recent content by berryfan

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    Maximum current and load regulation of a LDO supply current

    hi,thanks for all of you 1.if my LDO can supply 0~8mA current, and the load regulation is 7mV;but I only use 8mA ,so should I care the load regulation of 7mV 2.what is the maxium current which the LDO supply?I think it is related with the lowest supply voltage.
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    tsmc .18um cmos breakdown vlotage

    using TSMC .18um process,can I use 3.3V voltage ?eg.nmos:vds,vgs,vgd,vgb,vdb those voltage can be 3.6V?my nmos length can be large than 0.18um(for example 1u or 0.35um) thanks all
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    tsmc nmos2v mosfet can be used in 3.6V?

    there is one nmos2v mosfet i want to use it in 3.6V,can it breakdown?what's the breakdown condition?i find someone think the vgs is the important parameter.but I think the condition of all parameter vgs ,vdg,vgb,vdb. thank all~
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    tsmc .18um cmos breakdown vlotage

    can .18um CMOS using in VDD=3.3V? thanks,what's is the breakdown condition?
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    what max current should I supply in LDO

    hi~all if my LNA need 4mA(dc),I'm designing the LDO which supply the crrent to LNA,so how much current does the LDO need to supply?(I think is about 6mA)
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    the state of nmos or pmos in LDO

    checkmate,i mean that:should I keep the vgs>vth?in every load current
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    the state of nmos or pmos in LDO

    hi,all In LDO ,there is one mos which provide current to load.I'm adoubting that need I confirm that the state of mos is always in saturation? when load current is very low ,it's must not in "saturation region" thanks all ~ Added after 16 minutes: I have the nmos pass transistor,i get...
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    anybody suggestion on power management on chip

    3poles and 1zero,the second pole is load pole which changing by load current
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    Digital power management 's spec

    I have a digital power management named DVDDA,so I have some quesion to ask for help: 1.Imin~Imax:HOW to define the Imax(is it the max current which comes out in transient?I need to simulate the max current of my Digital current when I power on my vdd) AS in the fig,1,(2,3,4)?which is my max...
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    How to improve PSRR at high frequency?*(LDO)

    decoupling capacitor? from output to VDD?it must damage the PSRR and PM
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    How to improve PSRR at high frequency?*(LDO)

    my LDO PSRR,at 1K-80dB,but at 100K is -30dB.HOW can I improve my PSRR at 100KHz thanks
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    anybody suggestion on power management on chip

    how can I compensation LDO,when load current 0~20mA
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    anybody suggestion on power management on chip

    that is to say:what standard to justify the min-max current.for example:in VDD transit simulation,the maxim current is 30mA which is appear at start .so the max current is 30mA? thanks all of you
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    anybody suggestion on power management on chip

    in my system.it just a transient 0mA current load.it happens when my LDO is working ,then after several us my load current can increase a value.it just a very short time.must I consider this condition?

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