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Recent content by Basu_Gouda

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    Need n bit decoder for the construction of the sram

    Klaus Thank you for your response, you have seen it correctly my question is that i have to write the code for the entire decoding logic or can we design using n bit design in general. Thanks in advance - - - Updated - - - Klaus Thank you for your response, you have seen it correctly my...
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    Need n bit decoder for the construction of the sram

    yes you are pretty much correct i am doing the same, the thing i need to know is i have got 512 addresses to decode using 9 bits for each sub modules, so do i have to go for a 9 bit decoding logic fully or can i do it in general for n bits. thanks in advance
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    importance of w/l ratio

    If you want to know more about W/L ratio its better to refer Neil Weste "Digital CMOS Design: A system prespective". the W/L ratio plays an important role in deciding the current flow via a transistor and how to control the flow and as mentioned by andre yes the capacitance and resistance...
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    Need n bit decoder for the construction of the sram

    Hi I am designing a SOC for 32K * 8 bit sram with two level decoder hence i need to know whether we have anything for the n bit decoder or need to design the smaller decoder and combining them to get a bigger decoder. kindly help me out. thanks in advance
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    VGA display using fpga

    Re: VGA disply using fpga The design is for the Spartan XC6SLX9 using 100MHz clock frequency and a display of 640*480 pixels. The clk has been divided for 25MHz and used for the construction. The module is prepared with the guidance of " FPGA prototyping using verilog " book. Once debugged...
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    VGA display using fpga

    VGA disply using fpga Hi with respect to the above subject i am using a spartan 6 board to connect my acer tft display. the monitor when connected to the board is showing "input not supported" dialogue. please help me. thanks in advance.
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    [SOLVED] VGA controller for spartan 3

    Hi You are right the minimum clock input taken to the ip core of DCM as 18MHz. What is the alternative for this
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    [SOLVED] VGA controller for spartan 3

    Thanks for the reply it really helped me out. but now I have a issue that i have only 4MHz oscillator connected to my board is there anyway of using an internal clock or any other way to increase the clock as the display which i have chosen is needs 32MHz. Thanks in advance
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    [SOLVED] VGA controller for spartan 3

    Hi I am building an under water image processing system for which i need to display on the TFT through VGA, the problem is i dont have the kit which has built in VGA port in the PCB and hence I need to build on externally which I can connect to the i.o ports of the PCB. kindly guide me through...
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    initialization in verilog HDL

    Hi yes you are right, as i said earlier that it is just for checking up the functionality so you can just put your prediction for the start up values. even you can use the starting input as the inputs whatever you want in the testbench that is possible only you are sending certain no. of test...
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    initialization in verilog HDL

    Hello In stimulation if you want to start analyzing the functionality with specific start value the initial block is used. Where as the always block is always depends on the behavior of the functionality. Intialization is not synthesisable After synthesis the functionality you have written...
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    information on LT Spice Stimulator to work at home

    Hi all I am the user of mentor graphics design architect and eldo sim tool for my analog designs. Now i am working on LT spice at home can i use the libraries from different vendors for the construction of the analog designs. I want to know even is it possible to build large switch circuits...
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    synthesis error in ISE

    variable i : integer range 10 downto 0 := 0 I think you have initialized the signal to_uart like you did in the above variable i. What i meant to say is you cannot synthesize the code if you have initialized any variable with some predefined value do check for this
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    [SOLVED] practical cmos design of sample and hold circuit-- need help urgent

    Thanks for the reply at this moment I am focusing on building the high frequency opamp architecture I am unable find out the solution how to decide my mos sizes for the bandwidth
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    help in fpga based image processing project

    Yes you can. You can also interface your digicam and get the data and can be stimulated and can be connected to the VGA to display
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