Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Trouble when using "write_layout_scan" in DC and "detach scan chain" in Astro!:?:
In dc_shell-t,my design has been synthesized including "insert_scan",also,design.db and design.sv have been generated.
In order to get scan chain information for Astro,check_test、set_scan_configuration -prtool...
what is the meaning of shown below
**** WARNING: BPV on 8 macros were done with fatBlockageAsThin
the blockage inside these macros will be treated as thin
**** WARNING:Ignore 49 top-cell ports with no pins!
The two warnings came up from Astro.
What should I do to shoot them??
BTW:How...
In my design,
Core DC supply voltage:1.8V
I/O DC supply voltage: 3.3V
My IO and Core power pad in the reference library is:
IO power pad cell：PLVDDH
IO ground pad cell: PLVSSH
Core power pad cell: PLVDDC
Core ground pad cell: PLVSSC
and I want to:
connect Core power pad to global net VDD...
I have tried what you said,but it doesn't work.
My IO and Core power pad in the reference library is:
IO power pad cell：PLVDDH
IO ground pad cell: PLVSSH
Core power pad cell: PLVDDC
Core ground pad cell: PLVSSC
and I want to:
connect Core power pad to global net VDD
connect Core...
In "Timing setup" form,I have selected "worst" and "best" as Operating condition.
Warnings below ,however,came up when running "Timing Report" command.
WARNING : Operating condition worst does not exist
WARNING : Operating condition best does not exist
WARNING : Cannot set operating condition...
In Astro,how to deal with IO power pad and Core power pad with different voltage?
When expanding netlist,in Netlist In--->Exp--->Global Options,how to fill in the form?
I need a delay circuit in my design.And i know some methods,for example,registers,counter,buffer and cascade inverter.
But it 's not permitted to use registers and counter in my design.
therefore i could use buffer and cascade inverter.
i encountered a problem when i used buffer and cascade...
somebody help!
how to display an 26-bit binary digit in LED or LCD using decimal style.
in addition,the 26-bit binary digit is the output of an FPGA chip.
please tell me what should i do and how to describe it in vhdl?
thanks very much!!
i am waiting on line!
asic design flow diagram
somebody help me!! I have been looking for books and papers about asic design methodology and design flow for so long time!!who can tell me the design flow or give me some ideas?thank you a million times!!
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
