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Recent content by bageduke

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    Guard Ring Design - Closed loop or open loop?

    Guard ring is normally used for isolation between aggressor or victim. Long time ago, I was told that guard ring should be designed with a small opening, not a full closed loop pattern. Does anyone know the reason?
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    How to insert iprobe and still can pass LVS?

    Hi, I am running DC simulation for very large schematic to check leakage current/active DC current from each sub-blocks. (many of them share same power supply) Normally, in Cadence, people insert a VDC on top of each supply for every block so that they can see how the current is divided to...
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    Method for monitoring process variation of PMOS and NMOS

    I want to implement process monitor on chip. The easiest way is to count ring oscillator frequency to get process information. But in this case, I cannot tell it's PMOS or NMOS variation. Is there any simple way to monitor process variation of PMOS and NMOS separately? thanks
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    high speed (>10GHz), low power frequency divider needed

    Re: high speed (>10GHz), low power frequency divider need thanks for reply. Actually, I am looking for some on-chip circuit.
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    high speed (>10GHz), low power frequency divider needed

    Does anyone have frequency divider structure which can work at larger than 10GHz, but consume low power (Maybe "low power" word is not easy to justified)? Thanks,
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    Generate VDD independent voltage

    What is Norton Diodes? Do you have any circuit to show this structure?
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    Generate VDD independent voltage

    I want to generate a reference voltage which is very close to power supply level (say 1.3V supply and reference voltage at 1.1V), but the PSRR is relative high (say 30dB or above). Is there an easy way to do this? thanks,
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    How does spur change after frequency divider?

    Yes, you are right. In the case you mentioned, the spur will fold back. When I talked about un-changed spur offset frequency, I meant that like multi-GHz clock divided down to multi-GHz clock and spurs are at MHz offset. Sorry, I didn make it clear. Can you tell me, in this case, how does spur...
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    How does spur change after frequency divider?

    I have a question: How does spur change after frequency divider? I know that offset frequency won't change, but how about spur power level? Also unchange? Thanks,
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    papers for low drop, High PSRR on chip regulator

    The current load is not very high. Normally, it's about 6mA, so I am trying to design one can handle 10mA. Thanks, Kun
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    papers for low drop, High PSRR on chip regulator

    I am looking at at least 45dB PSRR at 3.2MHz. Thanks,
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    papers for low drop, High PSRR on chip regulator

    psrr and lowdrop Does anybody have papers for low drop, high PSRR on chip regulator? I want to design an on-chip regulator with 1.3V power supply and the PSRR is above 45dB with 0.2V drop. Thanks a lot
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    Offset PLL reading materials

    Thx a lot, vfone, you are always the one to help me in this forum!
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    Offset PLL reading materials

    Does anybody have materials about offset PLL design? Thanks,
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    IIP3s are different on left and right side of LO frequency

    Re: IIP3s are different on left and right side of LO frequen Yes, I tested it across the whole band - actually, the receiver is designed for wide band - it exhibits the same behavior, but the differences between left side and right side are different across the band.
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