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Hello,
I don't know really Assura tool but with Calibre from Mentor you need basically your layout (*.gds), your source netlist (*.sp) and in option a rule file.
In the rule file your are some information like where are your file on your computer the name of your output file(extracted netlist...
leda design rule checker
Hello,
You can generally find a lot of material about DRC in the doc of your verification tool.(for example in the repertory: /opt/Mentor/Calibre/docs/)
I use Calibre from Mentor Graphics and the doc useful for Design Rule Check is:
calbr_inter_user.pdf (interactive is...
dft basic example
Hello,
It was already written but can find a lot of materials on the support website of the major EDA companies if your company or uni has an access to the websupport.
For mentor it is here:
**broken link removed**
Have fun.
calibre site:edaboard.com
Hello,
you have normaly the doc of Calibre DRC/LVS (it is calibre interactive mentor product)in the /Calibre/docs/ repertory who is installed Calibre the name of the pdf doc is:
calbr_inter_user.pdf
Otherwise when you have access to the support of mentor go to...
Hello,
you have 3 connections in the layout netlist and just 2 in the source netlist.
You must so look at if there is an open in your layout.
This problem can actually have a link with VSS or VDD. It depends on how you have made your connect (real or virtual).
Check your layout(net name)...
I don't know but im munich as electronical student(I come from France) in the Uni for a master, it is possible to study and to work. The problem is davantage to study, to work and... to party ;oP
Have fun in Germany
Re: About C++ technology
C++ technologies stays (I think) for the moment the most used language because it owns a lot of standard libraries and the compiler are now relative effecient. C++ has been developped for 20 years so it has a lot of documentations and debug test.
For the futur I am not...
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