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Recent content by ayo_oc

  1. A

    MOS capacitance(Cgs probolem)

    thanks a lot! ---------- Post added at 12:24 ---------- Previous post was at 12:17 ---------- Please can you explain what you typed into the calculator? And do you think your method is sufficient to compute for example Cgs/micron width that can be used in quick hand analysis?
  2. A

    LNA design problem avago vmmk1218 noise figure and input matching

    If you want people to reply soon i would suggest you give more insight into the topology of LNA you are using instead of making people figure your question out first. What LNA topology are you using? If you are using a common gate LNA, the input matching is pretty straightforward, it is 1/gm. so...
  3. A

    MOS capacitance(Cgs probolem)

    But why don't you suggest how to do it in AC analysis? The point of people asking questions is to get an answer, not useless hints!
  4. A

    Two-stage amplifier in CMOS design

    Try cascoding the load. Then to get more gain, you can boost the transconductance of the loads also to increase the output resistance and thus the gain. Usually the best way is to split the gain about equally btw the 2 stages. To increase the unity gain frequency, you can add a resistor in...
  5. A

    transistor question????

    The purpose of C3 is to act as a by-pass capacitor for your amplifier, so effectively at high frequencies, the capacitor shunts the resistor and you have a common emmitter BJT amplifier. Also, in addition to using C3 as a bypass capacitor, if you choose the value properly, u might be able to use...
  6. A

    minimumphase transfer function

    I am sure all the poles and zeros has to be on the same side of plane! Now if you want a stable system in addition to minimum phase, obviously the poles and zeros have to be on the Left side of the plane. Since the question only asked for minimum phase and mentioned nothing about stability...
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    NMOS characterization in 0.25um Technology

    Hello guys, I am trying to characterize an NMOS transistor in 0.25um tech node to aid quick hand calculation in my design. My first task was to generate Vto (threshold voltage for zero source bulk bias). So i generated the I-V curve for the NMOS with W=10um and L=0.35um (I chose L > min, so i...
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