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Recent content by avin11

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    What and why is clock synthesis important?

    what is clock synthesis and why is it necessary?
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    how to check the functionality between cdl and verilog RTL ?

    Re: how to check the functionality between cdl and verilog R Whats formal verification ?
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    how to start with ASIC design ?

    When you mention ASIC design, it refes to the development stages involved in taping out the chip. Where digital is concerned, it involves synthesis process that tranforms your VHDL codes into gate netlist of a target library. Then static timing analysis is done to inspect the perf. and...
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    A question about the .lib file,how to generate it?

    hi, since you're using Synopsis DC for synthesis you would need the .DB file, which is generated from ur .LIB using Library Compiler. The .LIB file should be written by you and would contain the timing parameters and area of ur cells. Once completed, u must get it compiled using Library...
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    Doubts about junction capacitance values in Tanner l-edit

    Doubts with using Tanner hi, i've been using tanner l-edit for a while now. in the setup of the layers, the ndiff and pdiff extraction layers are filled with the junction capacitance values. When a circuit is extracted, does the parasitic capacitance of a node, say output, contain the junction...
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    How to calculate node cap in HSPICE?

    When a netlist is extracted for a layout, what does the parasitic capacitances represent? Please check me on this: - for input caps, it doesn't contain gate cap. but contains all routing caps for that input. When simulated in HSPICE, the gate cap is calculated by the tool and added to the...
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    Chinese open source ARM

    op source arm core Can someone please explain what is ARM and whats an opencore. My understanding is that the ARM processor is a RISC processor and opencore means the source code can be viewed whereas in most cases the code is hidden. Am I right?
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    Synopsys & Cadence tutorial

    What kind of tips do you need in detail?
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    Who can tell me how to build a library cell?

    What you want to do is that you want to use library cells to build a bigger system. Well isince you have a library, you can either manually route your design in layout level or you can place and route. To place and route you need to first draw schematic design and export its spice netlist. this...
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    Why synopsys gives up the FE?

    Syn@psis FPGA Compiler II I have a version. But do you have any softwares to share. I require a standard cell library of AMI or AMS or even the cadence IC design suit. Do you have any contacts for this. Anyway how can i share it with you?
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    Does anybody uses CircutSemant~cs tools? Like Dyna/Cell?

    What kind of characterization? I'm also doing digital cell characterization but not using those tools. Have u tried Silvaco SmartSpice?

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