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What and why is clock synthesis important?

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avin11

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what is clock synthesis and why is it necessary?
 

yeewang

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because you use clock everywhere in your design
 

zeese

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clock tree affects the delay & propagation of the signal
and the clock signal itself. Consequently, it affect the timing
of the circuit. If the timing is incorrect, the circuit will definitely
not working.
 

flypig

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because your design is in RTL level, and the clock can not be avoid to the design.
 

Shoaib

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to coordinate different components of circuit, and enable them to communicated properly with each other
 

eda_wiz

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zeese said:
clock tree affects the delay & propagation of the signal
and the clock signal itself. Consequently, it affect the timing
of the circuit. If the timing is incorrect, the circuit will definitely
not working.

It also determines the power consumption of chip.. Clock tree will take 30-50 % of the total chip power. Also unbalanced clock trees causes skews...in the design . which may lead to fast paths and finally improper functioanlity
 

farmerwang

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For synchronous design, we have the assumption that every FF is clocked at the same time. However, when goes to real gates, this is not true. You have to rely on CTS to control the skew within allowable range, use STA to verify it.
 

arpan_sen

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On the same lines, I want to know if we have
anyone in the group who can lead us to some known
algorithms for clock tree routing? I hear that
Steiner tree algorithms are quite popular.
Thanks in advance.
 

snaityma

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In RTL level simulation, it's ideal clock meaning zero skew,
But after routing, routing path & fan-out loading which cause clock skew.
When the clock skew over timing spec. it will cause function wrong!!
In many APR tools, they have clock synthesis utility. It's useful!!!
:) :eek:
 

trofim

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Now all vendor CAD have own APR tools
Mentor - Teraplace
Cadence - SESI or Encounter
Synopsys - Astro
 

sandusty

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Hi, arpan_sen:

They try to balance length in the early algorithms, for example, H-Tree

Steiner tree tried to balance load (wire load and input gate load). To find the steiner point has different algorithm. You can use n-ways partitioning/clustering to get the points.

Sometimes, people used clock mesh (!!!!) to reduce the skew (but burned power)

For more information, you can check the DAC proceeding in the late 90's. There are tons of those related algorithms.
 

sandusty

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Clock skew is not only caused by load.

Since the temperature, VDD will affect the clock buffer speed (from exp. there are more than 30 degree differences on an operating die), clock gen/CTS might caused more problems. (The place has more activities, normally it's the place of hot spot and lower VDD).

But no tool can take care above dynamic problem yet.
 

faisalali

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While making synchronous designs, we design the circuits with the assumption that all synchronous components using the same clock are clocked at the same instant. However, when these designs are synthesised this is not actually the case if proper care hasn't been taken during CTS. This particularly important in designs where pipelining is implemented. H-tree synthesis is one the most common example.
 

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