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sorry for pending late since i was on bussness.
welcome everyone.
let me introduce myself, i am a verification engineer for communation IC. i have used verilog, SV, and E for verification.
bit width convertor
if you just using a high level language (such C or SV), you can just assign 32'hM = 8'hM (M is the number), also M is a non-signed number
is for loop synthesizable
for Verilog HDL, as its name says, is a language to discribe a circuit. so you can't depend on the synthesise tool to generate your circuit before you design the circuit itselfe.
such as the code
For(i=0,i<k,i++)
have you seen such circuit? if you have not, how...
it is a trade off between the area and speed. so it is between the two kinds of array. systolic is faster but bigger, while general array is smaller but slower.
calculating fifo depth
to vinod488
i am not very clear. here is a question:
We have a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the...
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