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Recent content by asic_architect

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    How to fix errors in lint summary (check_timing_intent) during synthesis in Genus?

    Yes. For I/Os, I know the reasons are in SDC file (I/O delays). But "sequential clock pins..." I couldn`t find out more. Can you shed some light on the causes and commands? Tks!
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    How to fix errors in lint summary (check_timing_intent) during synthesis in Genus?

    I am getting following errors in check_timing_intent. Is there a way to fix them in Genus? Or I have to change the RTL? Lint summary Unconnected/logic driven clocks 0 Sequential data pins driven by a clock signal 0 Sequential clock pins without...
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    How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    Yes. I am struggling with Dynamic power (Internal power is 77% of total power). Power target after routing: 20uW Achieved power after synthesis: 370uW Can I bring it down that much during PnR somehow or should I change the libraries and synthesize again? How much power should I am at synthesis...
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    How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    Thanks for your response. I am already using HVTs though.
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    How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    No. I am not forcing Genus to use ICG. Heres my run details 1. A standard run script 2. See how much power you are getting 3. In the next run, to reduce the power I tried using "set_db lp_insert_clock_gating true" and got that message "libs dont have clock gating cells" Please let me know if...
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    How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    Genus says libs dont have clock gating cells.
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    How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    Hi, I have a RTL to synthesize and PnR with power as highest priority. Timing should just met. I dont have libs to support UPF or multi vdd, clock gating. I tried retiming at synthesis, but retimable flops are clocked with different clocks. Tools: Genus, Innovus Power target after routing in...
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    [SOLVED] How do I decide clock period constrain for Synthesis in DC?

    Thanks for the response. I have a quick follow ups I have done RTL to GDS flow for a project, but SDC, run script and all was already provided by professor. Now Im taking a random Open source RTL of a processor and trying to implement it from scratch. 1] Clock Period: I dont have the specs...
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    [SOLVED] How do I decide clock period constrain for Synthesis in DC?

    I have a RTL to synthesize in DC. How do I chose the value of various constraints like clock period, input/ output delay and multi cycle paths etc?
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    [SOLVED] How to load an already compiled design in Design Compiler?

    Thank you! That worked.
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    [SOLVED] How is physical design’s Intel flow different from regular RTL to GDS flow?

    I recently came across the term "Intel PD flow/ Intel flow" during my reading. Could any one shed some light on how it differs from the traditional RTL to GDS flow? Thanks!
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    [SOLVED] How to load an already compiled design in Design Compiler?

    Hello, I have already compiled a large design and wrote out .ddc. and exited DC. I am looking to do some optimizations on the same design. If I load that .ddc, I get different QoR than the original. I am just loading the .ddc. What am I doing wrong? Is there any other file I should load? Tks
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